JAJSIT3B March   2020  – April 2022 UCC27284

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History B
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable
      2. 7.3.2 Start-Up and UVLO
      3. 7.3.3 Input Stage
      4. 7.3.4 Level Shifter
      5. 7.3.5 Output Stage
      6. 7.3.6 Negative Voltage Transients
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Select Bootstrap and VDD Capacitor
        2. 8.2.2.2 Estimate Driver Power Losses
        3. 8.2.2.3 Selecting External Gate Resistor
        4. 8.2.2.4 Delays and Pulse Width
        5. 8.2.2.5 External Bootstrap Diode
        6. 8.2.2.6 VDD and Input Filter
        7. 8.2.2.7 Transient Protection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 Switching Characteristics

VDD = VHB = 12 V, VHS = VSS = 0 V, No load on LO or HO, TJ = –40°C to +140°C, (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
PROPAGATION DELAYS
tDLFFVLI falling to VLO fallingSee Section 6.7.1630ns
tDHFFVHI falling to VHO falling1630ns
tDLRRVLI rising to VLO rising1630ns
tDHRRVHI rising to VHO rising1630ns
DELAY MATCHING
tMONFrom LO being ON to HO being OFFSee Section 6.7.17ns
tMOFFFrom LO being OFF to HO being ON17ns
OUTPUT RISE AND FALL TIME
tRLO, HO rise timeCLOAD = 1800 pF, 10% to 90%12ns
tFLO, HO fall timeCLOAD = 1800 pF, 90% to 10%10ns
tRLO, HO (3 V to 9 V) rise timeCLOAD = 0.1 μF, 30% to 70%0.330.6μs
tFLO, HO (3 V to 9 V) fall timeCLOAD = 0.1 μF, 70% to 30%0.230.6μs
MISCELLANEOUS
TPW,minMinimum input pulse width that changes the output20ns
Bootstrap diode turnoff time(1)IF = 20 mA, IREV = 0.5 A50ns
(1) Parameter not tested in production