JAJSOL5B april   2023  – august 2023 UCC27301A-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 概要 (続き)
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Stages and Cross-Conduction Protection
      2. 8.3.2 Enable
      3. 8.3.3 Undervoltage Lockout (UVLO)
      4. 8.3.4 Level Shifter
      5. 8.3.5 Boot Diode
      6. 8.3.6 Output Stages
      7. 8.3.7 Negative Voltage Transients
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Threshold Type
        2. 9.2.2.2 VDD Bias Supply Voltage
        3. 9.2.2.3 Peak Source and Sink Currents
        4. 9.2.2.4 Propagation Delay
        5. 9.2.2.5 Power Dissipation
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 サード・パーティ製品に関する免責事項
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 用語集
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Package Option Addendum
      1.      54
    2. 13.2 Tape and Reel Information
    3. 13.3 Mechanical Data

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DRC|10
  • DDA|8
サーマルパッド・メカニカル・データ

6 Pin Configuration and Functions

GUID-2D8716D9-3FD7-490B-81B2-85A0148F7229-low.gif Figure 6-1 DDA Package 8-Pin SOIC with PowerPad™ Top View
GUID-437FF5C5-05C3-46E3-A59A-CE91CA18B644-low.gif Figure 6-2 DRC Package 10-Pin SON Top View
Table 6-1 Pin Functions
PIN TYPE(4) DESCRIPTION
NAME NO. (DDA) NO. (DRC)
EN N/A 6 I Enable input. When this pin is pulled high, it will enable the driver. If left floating or pulled low, it will disable the driver. A filter capacitor, typically 1-10nF, is recommended to be placed from EN to VSS (pin 7) to increase noise immunity in sensitive applications.
HB 2 3 P High-side bootstrap supply. The bootstrap diode is on-chip but the external bootstrap capacitor is required. Connect positive side of the bootstrap capacitor to this pin. Typical range of HB bypass capacitor is 0.022 µF to 0.1 µF. The capacitor value is dependant on the gate charge of the high-side MOSFET and must also be selected based on speed and ripple criteria.
HI 5 7 I High-side input.(1)
HO 3 4 O High-side output. Connect to the gate of the high-side power MOSFET.
HS 4 5 P High-side source connection. Connect to source of high-side power MOSFET. Connect the negative side of bootstrap capacitor to this pin.
LI 6 8 I Low-side input.(1)
LO 8 10 O Low-side output. Connect to the gate of the low-side power MOSFET.
VDD 1 1 P Positive supply to the lower-gate driver. Decouple this pin to VSS (GND). Typical decoupling capacitor range is 0.22 µF to 4.7 µF (see (2)).
VSS 7 9 G Negative supply terminal for the device that is generally grounded.
Thermal pad(3) — Electrically referenced to VSS (GND). Connect to a large thermal mass trace or GND plane to dramatically improve thermal performance.
(1) HI, LI, and EN inputs are assumed to connect to a low impedance source signal. The source output impedance is assumed less than 100 Ω. If the source impedance is greater than 100 Ω, add a bypassing capacitor, each, between HI to VSS, LI to VSS, and EN to VSS. The added capacitor value depends on the noise levels presented on the pins, typically from 1 nF to 10 nF should be effective to eliminate the possible noise effect. When noise is present on two pins, HI or LI, the effect is to cause HO and LO malfunctions to have wrong logic outputs.
(2) For cold temperature applications TI recommends the upper capacitance range. Follow the Layout Guidelines for PCB layout.
(3) The thermal pad is not directly connected to any leads of the package; however, it is electrically and thermally connected to the substrate which is the ground of the device.
(4) G = Ground, I = Input, O = Output, and P = Power.