JAJSOL5B april   2023  – august 2023 UCC27301A-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 概要 (続き)
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Stages and Cross-Conduction Protection
      2. 8.3.2 Enable
      3. 8.3.3 Undervoltage Lockout (UVLO)
      4. 8.3.4 Level Shifter
      5. 8.3.5 Boot Diode
      6. 8.3.6 Output Stages
      7. 8.3.7 Negative Voltage Transients
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Threshold Type
        2. 9.2.2.2 VDD Bias Supply Voltage
        3. 9.2.2.3 Peak Source and Sink Currents
        4. 9.2.2.4 Propagation Delay
        5. 9.2.2.5 Power Dissipation
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 サード・パーティ製品に関する免責事項
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 用語集
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Package Option Addendum
      1.      54
    2. 13.2 Tape and Reel Information
    3. 13.3 Mechanical Data

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DRC|10
  • DDA|8
サーマルパッド・メカニカル・データ

10 Power Supply Recommendations

The bias supply voltage range for which the device is recommended to operate is from 8 V to 17 V. The lower end of this range is governed by the internal undervoltage-lockout (UVLO) protection feature on the VDD pin supply circuit blocks. Whenever the driver is in UVLO condition when the VDD pin voltage is below the V(ON) supply start threshold, this feature holds the output low, regardless of the status of the inputs. The upper end of this range is driven by the 20-V absolute maximum voltage rating of the VDD pin of the device (which is a stress rating). Keeping a 3-V margin to allow for transient voltage spikes, the maximum recommended voltage for the VDD pin is 17 V. The UVLO protection feature also involves a hysteresis function, which means that when the VDD pin bias voltage has exceeded the threshold voltage and device begins to operate, and if the voltage drops, then the device continues to deliver normal functionality unless the voltage drop exceeds the hysteresis specification VDD(hys). Therefore, ensuring that, while operating at or near the 8-V range, the voltage ripple on the auxiliary power supply output is smaller than the hysteresis specification of the device is important to avoid triggering device shutdown. During system shutdown, the device operation continues until the VDD pin voltage has dropped below the V(OFF) threshold, which must be accounted for while evaluating system shutdown timing design requirements. Likewise, at system start-up the device does not begin operation until the VDD pin voltage has exceeded the V(ON) threshold.

The quiescent current consumed by the internal circuit blocks of the device is supplied through the VDD pin. Although this fact is well known, it is important to recognize that the charge for source current pulses delivered by the HO pin is also supplied through the same VDD pin. As a result, every time a current is sourced out of the HO pin, a corresponding current pulse is delivered into the device through the VDD pin. Thus, ensure that a local bypass capacitor is provided between the VDD and GND pins and located as close to the device as possible for the purpose of decoupling is important. A lo-ESR, ceramic surface-mount capacitor is required. TI recommends using a capacitor in the range 0.22 µF to 4.7 µF between VDD and GND. In a similar manner, the current pulses delivered by the LO pin are sourced from the HB pin. Therefore a 0.022-µF to 0.1-µF local decoupling capacitor is recommended between the HB and HS pins.