JAJSOL5B april   2023  – august 2023 UCC27301A-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 概要 (続き)
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Stages and Cross-Conduction Protection
      2. 8.3.2 Enable
      3. 8.3.3 Undervoltage Lockout (UVLO)
      4. 8.3.4 Level Shifter
      5. 8.3.5 Boot Diode
      6. 8.3.6 Output Stages
      7. 8.3.7 Negative Voltage Transients
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Threshold Type
        2. 9.2.2.2 VDD Bias Supply Voltage
        3. 9.2.2.3 Peak Source and Sink Currents
        4. 9.2.2.4 Propagation Delay
        5. 9.2.2.5 Power Dissipation
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 サード・パーティ製品に関する免責事項
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 用語集
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Package Option Addendum
      1.      54
    2. 13.2 Tape and Reel Information
    3. 13.3 Mechanical Data

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DRC|10
  • DDA|8
サーマルパッド・メカニカル・データ

8.1 Overview

The UCC27301A-Q1 is a high-voltage gate driver designed to drive both the high-side and the low-side N-channel MOSFETs in a synchronous buck or a half-bridge configurations. The two outputs are independently controlled with two TTL-compatible input signals. The device can also work with CMOS type control signals at its inputs as long as the signals meet the turn-on and turn-off threshold specifications of the device. The floating high-side driver is capable of operating with an HB voltage up to 115 V with respect to VSS. A 120-V bootstrap diode is integrated in the UCC27301A-Q1 device to charge the high-side gate drive bootstrap capacitor. A robust level shifter operates at high speed while consuming low power and provides clean level transitions from the control logic to the high-side gate driver. Undervoltage lockout (UVLO) is provided on both the low-side and the high-side power rails. EN pin is provided (in DRC packaged parts) to enable or disable the driver. The driver also has input interlock functionality, which shuts off both the outputs when the two inputs overlap.

In the UCC27301A-Q1 automotive device, the high side and low side have seperate, interlocked inputs that allow maximum flexibility of input control signals in the application. The boot diode for the high-side driver bias supply is internal to the UCC27301A-Q1.The high-side driver is referenced to the switch node (HS), which is typically the source pin of the high-side MOSFET and drain pin of the low-side MOSFET. The low-side driver is referenced to VSS, which is typically ground. The UCC27301A-Q1 functions are divided into the input stages, UVLO protection, level shift, boot diode, and output driver stages.

Table 8-1 UCC27301A-Q1 Highlights
FEATUREBENEFIT
+3.7-A/–4.5-A peak source and sink currentsHigh peak current ideal for driving large power MOSFETs with minimal power loss (fast-drive capability at Miller plateau)
Input pins (HI and LI) can directly handle –10 VDC up to 20 VDCIncreased robustness and ability to handle undershoot and overshoot can interface directly to gate-drive transformers without having to use rectification diodes.
120-V internal boot diodeProvides voltage margin to meet telecom 100-V surge requirements
Switch node (HS pin) able to handle –18 V maximum for 100 nsAllows the high-side channel to have extra protection from inherent negative voltages caused by parasitic inductance and stray capacitance
Robust ESD circuitry to handle voltage spikesExcellent immunity to large dV/dT conditions
16-ns/20-ns propagation delays with 7.2-ns rise time and 5.5-ns fall timeBest-in-class switching characteristics and extremely low-pulse transmission distortion
Cross-conduction protection Interlocks inputs to prevent shoot-through
Enable/disable functionalityOffers additional control over the driver for different system states (such as powerup sequencing) and a low quiescent current consumption when disabled
4-ns (typical) delay matching between channelsAvoids transformer volt-second offset in bridge
Symmetrical UVLO circuitEnsures high-side and low-side shut down at the same time
TTL optimized thresholds with increased hysteresisComplementary to analog or digital PWM controllers; increased hysteresis offers added noise immunity