SLUS704 Data sheet

SLUS704C FEBRUARY 2007 – December 2014 UCC27423-EP , UCC27424-EP

PRODUCTION DATA.

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

D|8
- MSOI002K

サーマルパッド・メカニカル・データ

発注情報

6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾⁽²⁾

over operating free-air temperature range (unless otherwise noted)

				MN	MAX	UNIT
V_DD	Supply voltage			–0.3	16	V
	Output current	OUTA, OUTB	DC, I_{OUT_DC}		0.2	A
	Output current	OUTA, OUTB	Pulsed (0.5 μs), I_{OUT_PULSED}		4.5	A
V_IN	Input voltage	INA, INB		–5	6 or V_DD + 0.3⁽³⁾	V
	Enable voltage	ENBA, ENBB		–0.3	6 or V_DD + 0.3⁽³⁾	V
	Power dissipation at T_A = 25°C	D package			650	mW
	Power dissipation at T_A = 25°C	DGN package			3	W
T_J	Junction operating temperature			–55	150	°C
	Lead temperature (soldering, 10 s)				300	°C
T_stg	Storage temperature			–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to GND. Currents are positive into and negative out of the specified terminal.

(3) Whichever is larger

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	±4000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	±1000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
T_J	Operating junction temperature	–55	125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		UCC27423-EP	UCC27424-EP	UNIT
		D	DGN
		8 PINS
R_θJA	Junction-to-ambient thermal resistance	111.4		°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	70.8
R_θJB	Junction-to-board thermal resistance	56.6
ψ_JT	Junction-to-top characterization parameter	10.9
ψ_JB	Junction-to-board characterization parameter	56.1

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Power Dissipation Ratings

PACKAGE	SUFFIX	R_θJC (°C/W)	R_θJA (°C/W)	POWER RATING (mW) T_A = 70°C	DERATING FACTOR ABOVE 70°C (mW/°C)
MSOP-8 PowerPAD⁽³⁾	DGN	4.7	50 to 59	1370⁽¹⁾	17.1⁽¹⁾
SOIC 8	D	42	84 to 160	344 to 655⁽²⁾⁽⁴⁾	6.25 to 11.9⁽²⁾⁽⁴⁾

(1) 150°C operating junction temperature is used for power-rating calculations.

(2) The range of values indicates the effect of PCB. These values are intended to give the system designer an indication of the best- and worst-case conditions. In general, the system designer should attempt to use larger traces on the PCB where possible, in order to spread the heat away from the device more effectively. For information on the PowerPAD package, refer to technical brief, PowerPad™ Thermally-Enhanced Package, SLMA002, and application brief, PowerPad™ Made Easy, SLMA004.

(3) The PowerPAD package is not directly connected to any leads of the package. However, it is electrically and thermally connected to the substrate, which is the ground of the device.

(4) 125°C operating junction temperature is used for power-rating calculation.

6.6 Electrical Characteristics

V_DD = 4.5 V to 15 V, T_A = –55°C to 125°C, T_A = T_J (unless otherwise noted)

PARAMETER		TEST CONDITIONS			UCC27423			UCC27424			UNIT
PARAMETER		TEST CONDITIONS			MIN	TYP	MAX	MIN	TYP	MAX	UNIT
INPUT (INA, INB)
V_{IN_H}	Logic 1 input threshold				2			2			V
V_{IN_L}	Logic 0 input threshold						1			1	V
	Input current	0 V ≤ V_IN ≤ V_DD			–10	0	10	–10	0	10	μA
OUTPUT (OUTA, OUTB)
	Output current	V_DD = 14 V⁽¹⁾⁽²⁾				4			4		A
V_OH	High-level output voltage	V_OH = V_DD – V_OUT, I_OUT = –10 mA				330	450		330	450	mV
V_OL	Low-level output level	I_OUT = 10 mA				22	40		22	40	mV
	Output resistance high	I_OUT = –10 mA, V_DD = 14 V⁽³⁾		T_A = 25°C	25	30	35	25	30	35	Ω
	Output resistance high	I_OUT = –10 mA, V_DD = 14 V⁽³⁾		T_A = full range	14		45	18		45	Ω
	Output resistance low	I_OUT = –10 mA, V_DD = 14 V⁽³⁾		T_A = 25°C	1.9	2.2	2.5	1.9	2.2	2.5	Ω
	Output resistance low	I_OUT = –10 mA, V_DD = 14 V⁽³⁾		T_A = full range	0.95		4	1.2		4	Ω
	Latch-up protection⁽¹⁾				500			500			mA
SWITCHING TIME
t_R	Rise time (OUTA, OUTB)	C_LOAD = 1.8 nF⁽¹⁾				20	40		20	40	ns
t_F	Fall time (OUTA, OUTB)	C_LOAD = 1.8 nF⁽¹⁾				15	40		15	40	ns
t_D1	Delay, IN rising (IN to OUT)	C_LOAD = 1.8 nF⁽¹⁾				35	55		35	50	ns
t_D2	Delay, IN falling (IN to OUT)	C_LOAD = 1.8 nF⁽¹⁾				25	60		25	45	ns
ENABLE (ENBA, ENBB)
V_{IN_H}	High-level input voltage	Low-to-high transition			1.7	2.4	3.1	1.7	2.4	2.9	V
V_{IN_L}	Low-level input voltage	High-to-low transition			1.1	1.8	2.3	1.1	1.8	2.2	V
	Hysteresis				0.13	0.55	1.1	.10	0.55	0.9	V
R_ENBL	Enable impedance	V_DD = 14 V,	ENBL = GND		75	100	160	75	100	140	kΩ
t_D3	Propagation delay time⁽⁴⁾	C_LOAD = 1.8 nF⁽¹⁾				30	60		30	60	ns
t_D4	Propagation delay time⁽⁴⁾	C_LOAD = 1.8 nF⁽¹⁾				100	150		100	150	ns
OVERALL
I_DD	Static operating current, V_DD = 15 V, ENBA = ENBB = 15 V	INA = 0 V	INB = 0 V			900	1350		300	450	μA
		INA = 0 V	INB = High			750	1100		750	1100
		INA = HIGH	INB = 0 V			750	1100		750	1100
		INA = HIGH	INB = High			600	900		1200	1800
	Disabled, V_DD = 15 V, ENBA = ENBB = 0 V	INA = 0 V	INB = 0 V			300	450		300	450
		INA = 0 V	INA = High			450	700		450	700
		INA = HIGH	INB = 0 V			450	700		450	700
		INA = HIGH	INB = High			600	900		600	900

(1) Specified by design. Not tested in production.

(2) The pullup/pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The pulsed output current rating is the combined current from the bipolar and MOSFET transistors.

(3) The pullup/pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The output resistance is the R_DS(ON) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor.

(4) See Figure 2.

A. The 10% and 90% thresholds depict the dynamics of the bipolar output devices that dominate the power MOSFET transition through the Miller regions of operation.

Figure 1. Switching Waveforms for (a) Inverting Driver and (b) Noninverting Driver

A. The 10% and 90% thresholds depict the dynamics of the bipolar output devices that dominate the power MOSFET transition through the Miller regions of operation.

Figure 2. Switching Waveform for Enable to Output