JAJSS81I September   2008  – November 2023 UCC27423-Q1 , UCC27424-Q1 , UCC27425-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Dissipation Ratings
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Stage
      2. 7.3.2 Output Stage
      3. 7.3.3 Enable
      4. 7.3.4 Parallel Outputs
      5. 7.3.5 Operational Waveforms and Circuit Layout
      6. 7.3.6 VDD
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Source and Sink Capabilities During Miller Plateau
        2. 8.2.2.2 Drive Current and Power Requirements
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 サード・パーティ製品に関する免責事項
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

VDD = 4.5 V to 15 V, TA = –40°C to 125°C, TA = TJ (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
INPUT (INA, INB)
VIHLogic 1 input threshold1.62.22.5V
VILLogic 0 input threshold0.81.21.5V
IINInput currentVIN = 0 V to VDD–10010μA
OUTPUT (OUTA, OUTB)
IOUTOutput currentVDD = 14 V(1) 4A
ROH Output resistance high IOUT = –10 mA, (2)1.22.5 Ω
ROL Output resistance low IOUT = 10 mA, (2)0.71.2 Ω
ENABLE (ENBA, ENBB)
VIN_HHigh-level input voltageLow-to-high transition1.72.42.9V
VIN_LLow-level input voltageHigh-to-low transition1.11.82.2V
Hysteresis0.150.550.9V
RENBLEnable impedanceVDD = 14 V, ENBL = GND75100145kΩ
OVERALL
IDDOperating currentStatic, VDD = 15 V, ENBA = ENBB = 15 VUCC27423-Q1INA = 0 VINB = 0 V9001350µA
INB = High7501100
INA = HighINB = 0 V7501100
INB = High600900
UCC27424-Q1INA = 0 VINB = 0 V300450
INB = High7501100
INA = HighINB = 0 V7501100
INB = High12001800
UCC27425-Q1INA = 0 VINB = 0 V600900
INB = High10501600
INA = HighINB = 0 V450700
INB = High9001350
Disabled, VDD = 15 V, ENBA = ENBB = 0 VAllINA = 0 VINB = 0 V300450
INB = High450700
INA = HighINB = 0 V450700
INB = High600900
(1) Parameter not tested in production
(2) Output pullup resistance in this table is a DC measurement that measures resistance of PMOS structure only (not N-channel structure).