JAJSC57F November   2002  – November 2023 UCC27423 , UCC27424 , UCC27425

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Dissipation Ratings
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable
      2. 7.3.2 Input Stage
      3. 7.3.3 Output Stage
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Source and Sink Capabilities During Miller Plateau
        2. 8.2.2.2 Parallel Outputs
        3. 8.2.2.3 VDD
        4. 8.2.2.4 Drive Current and Power Requirements
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 サード・パーティ製品に関する免責事項
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • D|8
  • P|8
  • DGN|8
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

VDD = 4.5 V to 15 V, TA = –40°C to 125°C,TA = TJ, (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
INPUT (INA, INB)
VIN_HLogic 1 input threshold1.62.22.5V
VIN_LLogic 0 input threshold0.81.21.5
Input current0 V ≤ VIN ≤ VDD–10010μA
OUTPUT (OUTA, OUTB)
Output currentVDD = 14 V (1)4A
ROH Output resistance high IOUT = –10 mA(2)1.22.5 Ω
ROL Output resistance low IOUT = 10 mA0.71.2
SWITCHING TIME
trRise time (OUTA, OUTB)CLOAD = 1.8 nF2040ns
tfFall time (OUTA, OUTB)CLOAD = 1.8 nF1540
td1Delay, IN rising (IN to OUT)CLOAD = 1.8 nF2540
td2Delay, IN falling (IN to OUT)CLOAD = 1.8 nF3550
ENABLE (ENBA, ENBB)
VIN_HHigh-level input voltageLO to HI transition1.72.42.9V
VIN_LLow-level input voltageHI to LO transition1.11.82.2V
Hysteresis0.150.550.90V
RENBEnable impedanceVDD = 14 V, ENB = GND75100140kΩ
tD3Propagation delay time (see Figure 6-3)CLOAD = 1.8 nF3060ns
tD4Propagation delay time (see Figure 6-3)CLOAD = 1.8 nF100150ns
OVERALL
IDDUCC27423
Static operating current, VDD = 15 V,
ENBA = ENBB = 15 V		INA = 0 V, INB = 0 V9001350μA
INA = 0 V, INB = HIGH7501100
INA = HIGH, INB = 0 V7501100
INA = HIGH, INB = HIGH600900
IDDUCC27424
Static operating current, VDD = 15 V,
ENBA = ENBB = 15 V		INA = 0 V, INB = 0 V300450μA
INA = 0 V, INB = HIGH7501100
INA = HIGH, INB = 0 V7501100
INA = HIGH, INB = HIGH12001800
IDDUCC27425
Static operating current, VDD = 15 V,
ENBA = ENBB = 15 V		INA = 0 V, INB = 0 V600900μA
INA = 0 V, INB = HIGH10501600
INA = HIGH, INB = 0 V450700
INA = HIGH, INB = HIGH9001350
IDDAll disabled, VDD = 15 V,
ENBA = ENBB = 0 V		INA = 0 V, INB = 0 V300450μA
INA = 0 V, INB = HIGH450700
INA = HIGH, INB = 0 V450700
INA = HIGH, INB = HIGH600900
(1) Parameter not tested in the production
(2) Output pullup resistance in this table is a DC measurement that measures resistance of PMOS structure only (not N-channel structure).