Table 2. UCC27517A-Q1 Summary

Table 3. UCC27517A-Q1 Features and Benefits

9.3.1 V_DD and Undervoltage Lockout

The UCC27517A-Q1 has internal Undervoltage Lockout (UVLO) protection feature on the V_DD-pin supply-circuit blocks. Whenever the driver is in UVLO condition (for example when V_DD voltage is less than V_ON during power up and when V_DD voltage is less than V_OFF during power down), this circuit holds all outputs LOW, regardless of the status of the inputs. The UVLO is typically 4.2 V with 300-mV typical hysteresis. This hysteresis helps prevent chatter when low V_DD – supply voltages have noise from the power supply and also when there are droops in the V_DD-bias voltage when the system commences switching and there is a sudden increase in I_DD. The capability to operate at low voltage levels such as below 5 V, along with best-in-class switching characteristics, is especially suited for driving emerging GaN wide-bandgap power-semiconductor devices.

For example, at power up, the UCC27517A-Q1 driver output remains LOW until the V_DD voltage reaches the UVLO threshold. The magnitude of the OUT signal rises with V_DD until steady-state V_DD is reached. In the non-inverting operation (PWM signal applied to IN+ pin) shown in Figure 19, the output remains LOW until the UVLO threshold is reached, and then the output is in-phase with the input. In the inverting operation (PWM signal applied to IN– pin) shown in Figure 20 the output remains LOW until the UVLO threshold is reached, and then the output is out-phase with the input. In both cases, the unused input pin must be properly biased to enable the output. Note that in these devices the output turns to high-state only if IN+ pin is high and IN– pin is low after the UVLO threshold is reached.

Because the driver draws current from the V_DD pin to bias all internal circuits, for the best high-speed circuit performance, two V_DD bypass capacitors are recommended to prevent noise problems. The use of surface-mount components is highly recommended. A 0.1-μF ceramic capacitor should be located as close as possible to the V_DD to GND pins of the gate driver. In addition, a larger capacitor (such as 1 μF) with relatively low ESR should be connected in parallel and close proximity, in order to help deliver the high-current peaks required by the load. The parallel combination of capacitors should present a low impedance characteristic for the expected current levels and switching frequencies in the application.

Figure 19. Power-Up (Non-Inverting Drive)

Figure 20. Power-Up (Inverting Drive)

9.3.2 Operating Supply Current

The UCC27517A-Q1 features very low quiescent I_DD currents. The typical operating-supply current in Undervoltage-Lockout (UVLO) state and fully-on state (under static and switching conditions) are summarized in Figure 5, Figure 6 and Figure 7. The I_DD current when the device is fully on and outputs are in a static state (DC high or DC low, refer Figure 7) represents lowest quiescent I_DD current when all the internal logic circuits of the device are fully operational. The total supply current is the sum of the quiescent I_DD current, the average I_OUT current due to switching and finally any current related to pullup resistors on the unused input pin. For example when the inverting input pin is pulled low additional current is drawn from V_DD supply through the pull-up resistors (refer to Detailed Description for the device Block Diagram). Knowing the operating frequency (f_SW) and the MOSFET gate (Q_G) charge at the drive voltage being used, the average I_OUT current can be calculated as product of Q_G and f_SW.

A complete characterization of the I_DD current as a function of switching frequency at different V_DD bias voltages under 1.8-nF switching load is provided in Figure 15. The strikingly-linear variation and close correlation with theoretical value of average I_OUT indicates negligible shoot-through inside the gate-driver device attesting to the high-speed characteristics of I_OUT.

9.3.3 Input Stage

The input pins of the UCC27517A-Q1 are based on a TTL and CMOS compatible input-threshold logic that is independent of the V_DD supply voltage. With typical high threshold = 2.2 V and typ low threshold = 1.2 V, the logic-level thresholds can be conveniently driven with PWM-control signals derived from 3.3-V and 5-V digital-power controllers. Wider hysteresis (typically 1 V) offers enhanced noise immunity compared to traditional TTL-logic implementations, where the hysteresis is typically less than 0.5 V. These devices also feature tight control of the input-pin threshold-voltage levels which eases system-design considerations and ensures stable operation across temperature. The very low input capacitance on these pins reduces loading and increases switching speed.

The device features an important protection function wherein, whenever any of the input pins are in a floating condition, the output of the respective channel is held in the low state. This is achieved using V_DD-pullup resistors on all the inverting inputs (IN– pin) or GND-pulldown resistors on all the non-inverting input pins (IN+ pin), (refer to the device Functional Block Diagram).

The device also features a dual-input configuration with two input pins available to control the state of the output. The user has the flexibility to drive the device using either a non-inverting input pin (IN+) or an inverting input pin (IN–). The state of the output pin is dependent on the bias on both the IN+ and IN– pins. Refer to the input/output logic truth table (Table 4) and the Typical Application Diagrams, (Figure 22 and Figure 23), for additional clarification.

Once an input pin has been chosen for PWM drive, the other input pin (the unused input pin) must be properly biased in order to enable the output. As mentioned earlier, the unused input pin cannot remain in a floating condition because, whenever any input pin is left in a floating condition, the output is disabled for protection purposes. Alternatively, the unused input pin can effectively be used to implement an enable/disable function, as explained below.

• In order to drive the device in a non-inverting configuration, apply the PWM-control input signal to IN+ pin. In this case, the unused input pin, IN–, must be biased low (eg. tied to GND) in order to enable the output.
  • Alternately, the IN– pin can be used to implement the enable/disable function using an external logic signal. OUT is disabled when IN– is biased high and OUT is enabled when IN– is biased low.
• In order to drive the device in an inverting configuration, apply the PWM-control input signal to IN– pin. In this case, the unused input pin, IN+, must be biased high (eg. tied to V_DD) in order to enable the output.
  • Alternately, the IN+ pin can be used to implement the enable/disable function using an external logic signal. OUT is disabled when IN+ is biased low and OUT is enabled when IN+ is biased high.
• Finally, note that the output pin is driven into a high state only when IN+ pin is biased high and IN– input is biased low.

The input stage of the driver should preferably be driven by a signal with a short rise or fall time. Caution must be exercised whenever the driver is used with slowly-varying input signals, especially in situations where the device is located in a mechanical socket or PCB layout is not optimal:

• High dI/dt current from the driver output coupled with board layout parasitics causes ground bounce. Because the device features just one GND pin, which may be referenced to the power ground, the differential voltage between input pins and GND is modified and triggers an unintended change of output state. Because of fast 13-ns propagation delay, high-frequency oscillations ultimately occur, which increases power dissipation and poses risk of damage.
• 1-V input-threshold hysteresis boosts noise immunity compared to most other industry-standard drivers.
• In the worst case, when a slow input signal is used and PCB layout is not optimal, adding a small capacitor (1 nF) between input pin and ground very close to the driver device is necessary. This helps to convert the differential mode noise with respect to the input-logic circuitry into common-mode noise and avoid unintended change of output state.

If limiting the rise or fall times to the power device is the primary goal, then an external resistance is highly recommended between the output of the driver and the power device instead of adding delays on the input signal. This external resistor has the additional benefit of reducing part of the gate charge related power dissipation in the gate-driver device package and transferring the gate driver into the external resistor.

9.3.4 Enable Function

As mentioned earlier, an enable or disable function is easily implemented in the UCC27517A-Q1 using the unused input pin. When IN+ is pulled down to GND or IN– is pulled down to V_DD, the output is disabled. Thus IN+ pin is used like an enable pin that is based on active-high logic, while IN– can be used like an enable pin that is based on active-low logic.

9.3.5 Output Stage

The UCC27517A-Q1 is capable of delivering 4-A source, 4-A sink (symmetrical drive) at V_DD = 12 V. The output stage of the UCC27517A-Q1 device is illustrated in Figure 21. The UCC27517A-Q1 features a unique architecture on the output stage which delivers the highest peak-source current when most needed during the Miller-plateau region of the power-switch turnon transition (when the power-switch drain/collector voltage experiences dV/dt). The device output stage features a hybrid pullup structure using a parallel arrangement of N-Channel and P-Channel MOSFET devices. By turning on the N-Channel MOSFET during a narrow instant when the output changes state from low to high, the gate-driver device delivers a brief boost in the peak-sourcing current enabling fast turnon.

Figure 21. UCC27517A-Q1 Gate Driver Output Structure

The R_OH parameter (see Electrical Characteristics) is a DC measurement and is representative of the on-resistance of the P-Channel device only, since the N-Channel device is turned on only during output change of state from low to high. Thus the effective resistance of the hybrid pullup stage is much lower than what is represented by R_OH parameter. The pulldown structure is composed of a N-Channel MOSFET only. The R_OL parameter (see Electrical Characteristics), which is also a DC measurement, is representative of true impedance of the pulldown stage in the device. In the UCC27517A-Q1, the effective resistance of the hybrid pullup structure is approximately 1.4 × R_OL.

The driver-output voltage swings between V_DD and GND providing rail-to-rail operation because of the MOS output stage which delivers very low dropout. The presence of the MOSFET-body diodes also offers low impedance to switching overshoots and undershoots. This means that in many cases, external Schottky-diode clamps may be eliminated. The outputs of these drivers are designed to withstand 500-mA reverse current without either damage to the device or logic malfunction.

9.3.6 Low Propagation Delays

The UCC27517A-Q1 features best-in-class input-to-output propagation delay of 13 ns (typ) at V_DD = 12 V. This promises the lowest level of pulse-transmission distortion available from industry-standard gate-driver devices for high-frequency switching applications. As seen in Figure 14, there is very little variation of the propagation delay with temperature and supply voltage as well, offering typically less than 20-ns propagation delays across the entire range of application conditions.

Table 4. Device Logic Table