JAJSUW2 June 2024 UCC27524
PRODUCTION DATA
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| BIAS CURRENTS (D, DGN) | ||||||
| IVDDq | VDD quiescent supply current | VINx = 3.3 V, VDD = 3.4 V, ENx = VDD | 300 | 450 | μA | |
| IVDD | VDD static supply current | VINx = 3.3 V, ENx = VDD | 0.6 | 1.0 | mA | |
| IVDD | VDD static supply current | VINx = 0 V, ENx = VDD | 0.7 | 1.0 | mA | |
| IVDDO | VDD operating current | fSW = 1000 kHz, ENx = VDD, VINx = 0 V – 3.3 V PWM | 3.2 | 3.8 | mA | |
| IDIS | VDD disable current | VINx = 3.3 V, ENx = 0 V | 0.8 | 1.1 | mA | |
| BIAS CURRENTS (DSD) | ||||||
| IDD(off) | Start-up current | VDD = 3.4 V, INA = VDD, INB = VDD |
55 | 110 | 175 | μA |
| VDD = 3.4 V, INA = GND, INB = GND |
25 | 75 | 145 | |||
| UNDERVOLTAGE LOCKOUT (UVLO) (D, DGN) | ||||||
| VVDD_ON | VDD UVLO rising threshold | 3.8 | 4.1 | 4.4 | V | |
| VVDD_OFF | VDD UVLO falling threshold | 3.5 | 3.8 | 4.1 | V | |
| VVDD_HYS | VDD UVLO hysteresis | 0.3 | V | |||
| UNDERVOLTAGE LOCKOUT (UVLO) (DSD) | ||||||
| VON | Supply start threshold | TJ = 25°C | 3.91 | 4.2 | 4.5 | V |
| TJ = –40°C to 140°C | 3.7 | 4.2 | 4.65 | |||
| VOFF | Minimum operating voltage after supply start | 3.4 | 3.9 | 4.4 | ||
| VDD_H | Supply voltage hysteresis | 0.2 | 0.3 | 0.5 | ||
| INPUT (INA, INB) (D, DGN) | ||||||
| VINx_H | Input signal high threshold | Output High, ENx = HIGH | 1.8 | 2 | 2.3 | V |
| VINx_L | Input signal low threshold | Output Low, ENx = HIGH | 0.8 | 1 | 1.2 | V |
| VINx_HYS | Input signal hysteresis | 1 | V | |||
| RINx | INx pin pulldown resistor | INx = 3.3 V | 120 | kΩ | ||
| INPUT (INA, INB) (DSD) | ||||||
| VIN_H | Input signal high threshold | Output high
for non-inverting input pins Output low for inverting input pins |
1.9 | 2.1 | 2.3 | V |
| VIN_L | Input signal low threshold | Output low
for non-inverting input pins Output high for inverting input pins |
1 | 1.2 | 1.4 | |
| VIN_HYS | Input hysteresis | 0.7 | 0.9 | 1.1 | ||
| ENABLE (ENA, ENB) (D, DGN) | ||||||
| VENx_H | Enable signal high threshold | Output High, INx = HIGH | 1.8 | 2 | 2.3 | V |
| VENx_L | Enable signal low threshold | Output Low, INx = HIGH | 0.8 | 1 | 1.2 | V |
| VENx_HYS | Enable signal hysteresis | 1 | V | |||
| RENx | EN pin pullup resistance | ENx = 0 V | 200 | kΩ | ||
| ENABLE (ENA, ENB) (DSD) | ||||||
| VEN_H | Enable signal high threshold | Output enabled | 1.9 | 2.1 | 2.3 | V |
| VEN_L | Enable signal low threshold | Output disabled | 0.95 | 1.15 | 1.35 | |
| VEN_HYS | Enable hysteresis | 0.7 | 0.95 | 1.1 | ||
| OUTPUTS (OUTA, OUTB) (D, DGN) | ||||||
| ISRC(1) | Peak output source current | VDD = 12 V, CVDD = 10 µF, CL = 0.1 µF, f = 1 kHz | 5 | A | ||
| ISNK(1) | Peak output sink current | VDD = 12 V, CVDD = 10 µF, CL = 0.1 µF, f = 1 kHz | –5 | A | ||
| ROH(2) | Pullup resistance | IOUT = –50 mA, See Section 7.3.4. | 5 | 8.5 | Ω | |
| ROL | Pulldown resistance | IOUT = 50 mA | 0.6 | 1.1 | Ω | |
| OUTPUTS (OUTA, OUTB) (DSD) | ||||||
| ISNK/SRC(1) | Sink/source peak current | CLOAD = 0.22 µF, FSW = 1 kHz | ±5 | A | ||
| VDD-VOH | High output voltage | IOUT = –10 mA | 0.075 | V | ||
| VOL | Low output voltage | IOUT = 10 mA | 0.01 | |||
| ROH(2) | Output pullup resistance | IOUT = –10 mA | 2.5 | 5 | 7.5 | Ω |
| ROL | Output pulldown resistance | IOUT = 10 mA | 0.15 | 0.5 | 1 | Ω |