SLVSCC1C November   2013  – June 2024 UCC27524A-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Description (continued)
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Operating Supply Current
      2. 7.3.2 Input Stage
      3. 7.3.3 Enable Function
      4. 7.3.4 Output Stage
    4. 7.4 Low Propagation Delays and Tightly Matched Outputs
    5. 7.5 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 VDD and Undervoltage Lockout
        2. 8.2.2.2 Drive Current and Power Dissipation
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

UCC27524A-Q1 D and DGN Packages8-Pin SOIC and HVSSOP-PowerPADTop View Figure 5-1 D and DGN Packages8-Pin SOIC and HVSSOP-PowerPADTop View
Table 5-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
ENA 1 I Enable input for Channel A: ENA is biased LOW to disable the Channel A output regardless of the INA state. ENA is biased HIGH or left floating to enable the Channel A output. ENA is allowed to float; hence the pin-to-pin compatibility with the UCC2732X N/C pin.
ENB 8 I Enable input for Channel B: ENB is biased LOW to disables the Channel B output regardless of the INB state. ENB is biased HIGH or left floating to enable Channel B output. ENB is allowed to float hence; the pin-to-pin compatibility with the UCC2732X N/C pin.
GND 3 - Ground: All signals are referenced to this pin.
INA 2 I Input to Channel A: INA is the non-inverting input in the UCC27524A-Q1 device. OUTA is held LOW if INA is unbiased or floating.
INB 4 I Input to Channel B: INB is the non-inverting input in the UCC27524A-Q1 device. OUTB is held LOW if INB is unbiased or floating.
OUTA 7 O Output of Channel A
OUTB 5 O Output of Channel B
VDD 6 I Bias supply input