SNVSA89A December   2014  – May 2015 UCC27528-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDD and Undervoltage Lockout
      2. 8.3.2 Operating Supply Current
      3. 8.3.3 Input Stage
      4. 8.3.4 Enable Function
      5. 8.3.5 Output Stage
      6. 8.3.6 Low Propagation Delays and Tightly Matched Outputs
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input-to-Output Logic
        2. 9.2.2.2 Enable and Disable Function
        3. 9.2.2.3 VDD Bias Supply Voltage
        4. 9.2.2.4 Propagation Delay
        5. 9.2.2.5 Drive Current and Power Dissipation
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Specifications

7.1 Absolute Maximum Ratings(1)(2)

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Supply voltage range VDD –0.3 20 V
INA, INB, voltage(3) –6.5 20 V
ENA, ENB voltage(3) –0.3 20 V
OUTA, OUTB voltage DC –0.3 VDD + 0.3 V
Repetitive pulse < 200 ns(4) –2 VDD + 0.3
Output continuous source and sink current IOUT_DC 0.3 A
Output pulsed source and sink current (0.5 µs) IOUT_pulsed 5 A
Operating virtual junction temperature, TJ –40 150 °C
Lead temperature Soldering, 10 s 300 °C
Reflow 260
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND unless otherwise noted. Currents are positive into, negative out of the specified terminal. See Packaging Section of the datasheet for thermal limitations and considerations of packages.
(3) The maximum voltage on the Input and Enable pins is not restricted by the voltage on the VDD pin.
(4) Values are verified by characterization on bench.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±4000 V
Charged-device model (CDM), per AEC Q100-011 ±1000
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD Supply voltage 4.5 12 18 V
Input voltage INA, INB –5 18 V
Enable voltage ENA and ENB 0 18 V
Operating junction temperature –40 140 °C

7.4 Thermal Information

THERMAL METRIC(1) D UNIT
8 PINS
RθJA Junction-to-ambient thermal resistance 128 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 77.7
RθJB Junction-to-board thermal resistance 68.5
ψJT Junction-to-top characterization parameter 20.7
ψJB Junction-to-board characterization parameter 68
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

VDD = 12 V, TA = TJ = –40 °C to 140 °C, 1-µF capacitor from VDD to GND. Currents are positive into, negative out of the specified terminal (unless otherwise noted,)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BIAS CURRENTS
IDD(off) Startup current VDD = 3.4 V, INA = VDD, INB = VDD 55 125 225 μA
VDD = 3.4 V, INA = GND, INB = GND 25 125 225
UNDERVOLTAGE LOCKOUT (UVLO)
VON Supply start threshold TJ = 25°C 3.91 4.2 4.5 V
TJ = –40°C to 140°C 3.75 4.2 4.65
VOFF Minimum operating voltage after supply start 3.6 3.9 4.4
VDD_H Supply voltage hysteresis 0.2 0.3 0.5
INPUTS (INA, INB)
VIN_H Input signal high threshold Output high for non-inverting input pins
Output low for inverting input pins		 55 70 %VDD
VIN_L Input signal low threshold Output low for non-inverting input pins
Output high for inverting input pins		 30 38
VIN_HYS Input hysteresis 17
ENABLE (ENA, ENB)
VEN_H Enable signal high threshold Output enabled 1.7 1.9 2.1 V
VEN_L Enable signal low threshold Output disabled 0.95 1.10 1.25
VEN_HYS Enable hysteresis 0.7 0.8 1.1
OUTPUTS (OUTA, OUTB)
ISNK/SRC Sink and source peak current(1) CLOAD = 0.22 µF, fSW = 1 kHz ±5 A
VDD–VOH High output voltage IOUT = –10 mA 0.075 V
VOL Low output voltage IOUT = 10 mA 0.01
ROH Output pullup resistance(2) IOUT = –10 mA 2.5 5 7.5 Ω
ROL Output pulldown resistance IOUT = 10 mA 0.15 0.5 1 Ω
(1) Ensured by design.
(2) ROH represents on-resistance of only the P-Channel MOSFET device in pullup structure of UCC27528-Q1 output stage.

7.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tR Rise time CLOAD = 1.8 nF, VDD = 10 V 7 ns
tF Fall time CLOAD = 1.8 nF, VDD = 10 V 6 ns
tM Delay matching between 2 channels INA = INB, OUTA and OUTB at 50% transition point, VDD = 10 V 1 4 ns
tPW Minimum input pulse width that changes the output state VDD = 10 V 15 ns
tD1, tD2 Input to output propagation delay, See Figure 2. CLOAD = 1.8 nF, 7-V input pulse,
VDD = 10 V		 6 17 26 ns
tD3, tD4 EN to output propagation delay,
See Figure 1 .		 CLOAD = 1.8 nF, 7-V enable pulse, VDD = 10 V 6 13 23 ns
UCC27528-Q1 timing1_snvsa89.gifFigure 1. Enable Function
(Non-Inverting Input Driver Operation)
UCC27528-Q1 timing3_snvsa89.gifFigure 2. Non-Inverting Input Driver Operation

7.7 Typical Characteristics

UCC27528-Q1 wav10_snvsa89.gif
VDD = 3.4 V
Figure 3. Startup Current vs Temperature
UCC27528-Q1 wav12_snvsa89.gif
VDD = 12 V
Figure 5. Supply Current vs Temperature (Outputs In DC On/Off Condition)
UCC27528-Q1 wav14_snvsa89.gif
VDD = 12 V
Figure 7. Input Threshold vs Temperature
UCC27528-Q1 wav16_snvsa89.gif
VDD = 12 V IOUT = 10 mA
Figure 9. Output Pullup Resistance vs Temperature
UCC27528-Q1 wav18_snvsa89.gif
VDD = 10 V CLOAD = 1.8 nF
Figure 11. Rise Time vs Temperature
UCC27528-Q1 wav20_snvsa89.gif
VDD = 10 V
Figure 13. Input To Output Propagation Delay vs Temperature
UCC27528-Q1 wav22_snvsa89.gif
Both Channels Switching CLOAD = 1.8 nF
Figure 15. Operating Supply Current vs Frequency
UCC27528-Q1 wav24_snvsa89.gif
CLOAD = 1.8 nF
Figure 17. Rise Time vs Supply Voltage
UCC27528-Q1 G017_EnableThreshold_4.5V_snvsa89.gif
VDD = 4.5 V
Figure 19. Enable Threshold vs Temperature
UCC27528-Q1 wav11_snvsa89.gif
VDD = 12 V CLOAD = 500 pF Both Channels Switching
fSW = 500 kHz
Figure 4. Operating Supply Current vs Temperature (Outputs Switching)
UCC27528-Q1 wav13_snvsa89.gif
Figure 6. UVLO Threshold vs Temperature
UCC27528-Q1 wav15_snvsa89.gif
VDD = 12 V
Figure 8. Enable Threshold vs Temperature
UCC27528-Q1 wav17_snvsa89.gif
VDD = 12 V IOUT = 10 mA
Figure 10. Output Pulldown Resistance vs Temperature
UCC27528-Q1 wav19_snvsa89.gif
VDD = 10 V CLOAD = 1.8 nF
Figure 12. Fall Time vs Temperature
UCC27528-Q1 wav21_snvsa89.gif
VDD = 10 V
Figure 14. En To Output Propagation Delay vs Temperature
UCC27528-Q1 wav23_snvsa89.gif
CLOAD = 1.8 nF
Figure 16. Propagation Delays vs Supply Voltage
UCC27528-Q1 wav25_snvsa89.gif
CLOAD = 1.8 nF
Figure 18. Fall Time vs Supply Voltage