JAJST72A April   2024  – October 2024 UCC27614-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 VDD Undervoltage Lockout
      2. 6.3.2 Input Stage
      3. 6.3.3 Enable Function
      4. 6.3.4 Output Stage
    4. 6.4 Device Functional Modes
  8. 7  Applications and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Driving MOSFET/IGBT/SiC MOSFET
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Input-to-Output Configuration
          2. 7.2.1.2.2 Input Threshold Type
          3. 7.2.1.2.3 VDD Bias Supply Voltage
          4. 7.2.1.2.4 Peak Source and Sink Currents
          5. 7.2.1.2.5 Enable and Disable Function
          6. 7.2.1.2.6 Propagation Delay and Minimum Input Pulse Width
          7. 7.2.1.2.7 Power Dissipation
        3. 7.2.1.3 Application Curves
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
    3. 9.3 Thermal Consideration
  11. 10Device and Documentation Support
    1. 10.1 サード・パーティ製品に関する免責事項
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

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発注情報

6.1 Overview

The UCC27614-Q1 device is a single-channel, high-speed, gate drivers capable of effectively driving MOSFET, SiC MOSFET, and IGBT power switches with 10-A source and 10-A sink (symmetrical drive) peak current. A strong source and sink capability boost immunity against a parasitic Miller turnon effect. The UCC27614-Q1 device can be directly connected to the gate driver transformer or line driver transformer as the inputs of the UCC27614-Q1 can handle –10V. The driver has a good transient handling capability on its output due to reverse currents, as well as rail-to-rail drive capability and small propagation delay, typically 17.5 ns.

The input threshold of the UCC27614-Q1 is compatible to TTL low-voltage logic, which is fixed and independent of VDD supply voltage. The driver can also work with CMOS based controllers as long as the threshold requirement is met. The 1-V typical hysteresis offers excellent noise immunity.

The driver has an EN pin with fixed TTL compatible threshold. EN is internally pulled up; pulling EN low disables the driver, while leaving EN open provides normal operation. The EN pin can be used as an additional input with the same performance as the IN, IN+, and IN- pins.

Table 6-1 UCC27614-Q1 Features and Benefits
FEATURE BENEFIT
–10 V IN and EN capability Enhanced signal reliability and device robustness in noisy environments that experience ground bounce on the gate driver.
High source and sink current capability, 10 A High current capability helps drive large gate charge loads to minimize switching losses.
Low 17.5 ns (typ) propagation delay. Extremely low pulse transmission distortion
Wide VDD operating range of 4.5 V to 26 V Flexibility in system design
VDD UVLO protection Outputs are held Low in UVLO condition, which ensures predictable, glitch-free operation at power up and power down.
UVLO of 4 V (typical) allows use in high switching frequency applications at low bias voltage to reduce switching losses.
Outputs held low when input pin (INx) in floating condition Safety feature, especially useful in passing abnormal condition tests during safety certification

EN can float

Safe operation when the output of the controller, ties to the EN pin in tristate
Strong sink current (10 A) and low pulldown impedance (0.34 Ω) High immunity to high dV/dt Miller turnon events
TTL compatible input threshold logic with wide hysteresis Enhanced noise immunity, while retaining compatibility with microcontroller logic level input signals (3.3 V, 5 V) optimized for digital power