JAJST72A April   2024  – October 2024 UCC27614-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 VDD Undervoltage Lockout
      2. 6.3.2 Input Stage
      3. 6.3.3 Enable Function
      4. 6.3.4 Output Stage
    4. 6.4 Device Functional Modes
  8. 7  Applications and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Driving MOSFET/IGBT/SiC MOSFET
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Input-to-Output Configuration
          2. 7.2.1.2.2 Input Threshold Type
          3. 7.2.1.2.3 VDD Bias Supply Voltage
          4. 7.2.1.2.4 Peak Source and Sink Currents
          5. 7.2.1.2.5 Enable and Disable Function
          6. 7.2.1.2.6 Propagation Delay and Minimum Input Pulse Width
          7. 7.2.1.2.7 Power Dissipation
        3. 7.2.1.3 Application Curves
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
    3. 9.3 Thermal Consideration
  11. 10Device and Documentation Support
    1. 10.1 サード・パーティ製品に関する免責事項
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DSG|8
サーマルパッド・メカニカル・データ
発注情報

5.5 Electrical Characteristics

Unless otherwise noted, VDD = 12 V, TA = TJ = –40°C to 150°C, 1-µF capacitor from VDD to GND, No load on the output. Typical condition specifications are at 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BIAS CURRENTS
IVDDq VDD quiescent supply current VIN+/VIN = 3.3 V, VIN- = 0 V, EN=VDD, VDD = 3.4 V 305 500 μA
IVDD VDD static supply current VIN+/VIN = 3.3 V, VIN- = 0 V, EN = VDD 0.64 0.92 mA
IVDD VDD static supply current VIN+/VIN = 0 V, VIN- = 0 V, EN = VDD 0.71 1.0 mA
IVDDO VDD dynamic operating current fSW = 1000 kHz, EN = VDD, VIN+/VIN = 0 V to 3.3 V PWM, VIN- = 0 V 4.0 mA
IDIS VDD disable current VIN+/VIN = 0 V, VIN- = 3.3 V, EN = 0 V 0.75 1.0 mA
UNDERVOLTAGE LOCKOUT (UVLO)
VVDD_ON VDD UVLO rising threshold 3.8 4.1 4.4 V
VVDD_OFF VDD UVLO falling threshold 3.5 3.8 4.1 V
VVDD_HYS VDD UVLO hysteresis 0.3 V
INPUT (IN, IN+)
VIN_H Input signal high threshold, output high Output high, IN- = LOW, EN=HIGH 1.8 2 2.3 V
VIN_L Input signal low threshold, output low Output low, IN- = LOW, EN=HIGH 0.8 1 1.2 V
VIN_HYS Input signal hysteresis 1 V
RIN INx pin Pulldown resistance IN+/IN = 3.3 V 120 kΩ
INPUT (IN-)
VIN-_H Input signal high threshold, output low Output low, IN+ = HIGH, EN = high 1.8 2 2.3 V
VIN-_L Input signal low threshold, output high Output high, IN+ = HIGH, EN = high 0.8 1 1.2 V
VIN-_HYS Input signal hysteresis 1 V
RIN- IN- pin pullup resistance IN- = 0 V 200 kΩ
ENABLE (EN)
VEN_H Enable signal high threshold Output high, IN+/IN = high, IN- =0 V 1.8 2 2.3 V
VEN_L Enable signal low threshold Output low, IN+/IN = high, IN- = 0 V 0.8 1 1.2 V
VEN_HYS Enable signal hysteresis 1 V
REN EN pin pullup resistance EN = 0 V 200 kΩ
OUTPUT (OUT)
ISRC(1) Peak output source current VDD = 12 V, CVDD = 10 µF, CL = 0.1 µF, f = 1 kHz 10 A
ISNK(1) Peak output sink current VDD = 12 V, CVDD = 10 µF, CL = 0.1 µF, f = 1 kHz –10 A
ROH(2) OUTH, pullup resistance IOUT = –50 mA

See: Section 6.3.4

 2.5 4.5 Ω
ROL OUTL, pulldown resistance IOUT = 50 mA 0.34 0.55 Ω
(1) Parameter not tested in production.
(2) Output pullup resistance here is a DC measurement that measures resistance of PMOS structure only, not N-channel structure.