JAJST72A April   2024  – October 2024 UCC27614-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 VDD Undervoltage Lockout
      2. 6.3.2 Input Stage
      3. 6.3.3 Enable Function
      4. 6.3.4 Output Stage
    4. 6.4 Device Functional Modes
  8. 7  Applications and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Driving MOSFET/IGBT/SiC MOSFET
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Input-to-Output Configuration
          2. 7.2.1.2.2 Input Threshold Type
          3. 7.2.1.2.3 VDD Bias Supply Voltage
          4. 7.2.1.2.4 Peak Source and Sink Currents
          5. 7.2.1.2.5 Enable and Disable Function
          6. 7.2.1.2.6 Propagation Delay and Minimum Input Pulse Width
          7. 7.2.1.2.7 Power Dissipation
        3. 7.2.1.3 Application Curves
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
    3. 9.3 Thermal Consideration
  11. 10Device and Documentation Support
    1. 10.1 サード・パーティ製品に関する免責事項
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DSG|8
サーマルパッド・メカニカル・データ
発注情報

6.4 Device Functional Modes

The UCC27614-Q1 devices operate in normal mode and UVLO mode (see Section 6.3.1 for information on UVLO operation). In normal mode, the output state is dependent on the states of the device, and the input pins.

The UCC27614-Q1 DSG features dual input, one inverting (IN-), and one non-inverting (IN+). This device does not contain a dedicated enable (EN) pin as in the UCC27614-Q1 D and DGN.

The UCC27614-Q1 D and DGN feature a single, non-inverting input, but also contain enable and disable functionality through the EN pin. Setting the EN pin to logic HIGH enables the non-inverting input to output on the IN pin. The two OUT pins are internally shorted and shall be shorted on the application board as well.

Table 6-2 UCC27614-Q1DSG Truth Table

IN+

IN-

OUT

H

L

H

H

H

L

L

H

L

L

L

L

Float

Any

L

Any

Float

L
Table 6-3 UCC27614-Q1D and DGN Truth Table

IN

EN

OUT

H

L

L

H

H

H

L

H

L

L

L

L

Float

Any

L

Any

Float

IN