JAJSMZ6 december   2021 UCC28781

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 説明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Detailed Pin Description
      1. 7.3.1  BUR Pin (Programmable Burst Mode)
      2. 7.3.2  FB Pin (Feedback Pin)
      3. 7.3.3  REF Pin (Internal 5-V Bias)
      4. 7.3.4  VDD Pin (Device Bias Supply)
      5. 7.3.5  P13 and SWS Pins
      6. 7.3.6  S13 Pin
      7. 7.3.7  IPC Pin (Intelligent Power Control Pin)
      8. 7.3.8  RUN Pin (Driver and Bias Source for Isolator)
      9. 7.3.9  PWMH and AGND Pins
      10. 7.3.10 PWML and PGND Pins
      11. 7.3.11 SET Pin
      12. 7.3.12 RTZ Pin (Sets Delay for Transition Time to Zero)
      13. 7.3.13 RDM Pin (Sets Synthesized Demagnetization Time for ZVS Tuning)
      14. 7.3.14 XCD Pin
      15. 7.3.15 CS, VS, and FLT Pins
    4. 7.4 Device Functional Modes
      1. 7.4.1  Adaptive ZVS Control with Auto-Tuning
      2. 7.4.2  Dead-Time Optimization
      3. 7.4.3  EMI Dither and Dither Fading Function
      4. 7.4.4  Control Law Across Entire Load Range
      5. 7.4.5  Adaptive Amplitude Modulation (AAM)
      6. 7.4.6  Adaptive Burst Mode (ABM)
      7. 7.4.7  Low Power Mode (LPM)
      8. 7.4.8  First Standby Power Mode (SBP1)
      9. 7.4.9  Second Standby Power Mode (SBP2)
      10. 7.4.10 Startup Sequence
      11. 7.4.11 Survival Mode of VDD (INT_STOP)
      12. 7.4.12 System Fault Protections
        1. 7.4.12.1  Brown-In and Brown-Out
        2. 7.4.12.2  Output Over-Voltage Protection (OVP)
        3. 7.4.12.3  入力過電圧保護 (IOVP)
        4. 7.4.12.4  FLT ピンの過熱保護 (OTP)
        5. 7.4.12.5  CS ピンの過熱保護 (OTP)
        6. 7.4.12.6  プログラム可能な過電力保護 (OPP)
        7. 7.4.12.7  ピーク電力制限 (PPL)
        8. 7.4.12.8  出力短絡保護 (SCP)
        9. 7.4.12.9  過電流保護 (OCP)
        10. 7.4.12.10 External Shutdown
        11. 7.4.12.11 Internal Thermal Shutdown
      13. 7.4.13 Pin Open/Short Protections
        1. 7.4.13.1 Protections on CS pin Fault
        2. 7.4.13.2 Protections on P13 pin Fault
        3. 7.4.13.3 Protections on RDM and RTZ pin Faults
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application Circuit
      1. 8.2.1 Design Requirements for a 60-W, 15-V ZVSF Bias Supply Application with a DC Input
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Bulk Capacitance and Minimum Bulk Voltage
        2. 8.2.2.2 Transformer Calculations
          1. 8.2.2.2.1 Primary-to-Secondary Turns Ratio (NPS)
          2. 8.2.2.2.2 Primary Magnetizing Inductance (LM)
          3. 8.2.2.2.3 Primary Winding Turns (NP)
          4. 8.2.2.2.4 Secondary Winding Turns (NS)
          5. 8.2.2.2.5 Auxiliary Winding Turns (NA)
          6. 8.2.2.2.6 Winding and Magnetic Core Materials
        3. 8.2.2.3 Calculation of ZVS Sensing Network
        4. 8.2.2.4 Calculation of BUR Pin Resistances
        5. 8.2.2.5 Calculation of Compensation Network
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1  General Considerations
      2. 10.1.2  RDM and RTZ Pins
      3. 10.1.3  SWS Pin
      4. 10.1.4  VS Pin
      5. 10.1.5  BUR Pin
      6. 10.1.6  FB Pin
      7. 10.1.7  CS Pin
      8. 10.1.8  AGND Pin
      9. 10.1.9  PGND Pin
      10. 10.1.10 Thermal Pad
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Receiving Notification of Documentation Updates
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 用語集
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 Typical Characteristics

VVDD = 20 V, RRDM = 115 kΩ, RRTZ = 140 kΩ, VSET = 0 V, and TJ = TA = 25 ⁰C (unless otherwise noted)

GUID-8BAEB66E-0AFE-439B-B965-6EA544A1D355-low.gif
Figure 6-1 VDD Bias-Supply Current vs. VDD Bias-Supply Voltage
GUID-9F3E5F0A-6A8A-481F-BE95-6CBD8B698541-low.gif
Figure 6-3 VS Line-Sense Currents vs. Temperature
GUID-6CA0503E-05A9-4F19-AEB5-2F1B254018CB-low.gif
Figure 6-5 CS Peak-Power Threshold for VVS > VVSLV(UP) vs. VS Line-Sense Currents
GUID-B120A295-C383-4F7B-B1E2-0992BE8E81F5-low.gif
Figure 6-7 tZ Compensation Ratio (KTZ) vs. VS Line-Sense Currents
GUID-38D4A1CB-5325-45E3-846E-A7523FDA28AD-low.gif
Figure 6-9 REF Voltage vs. Temperature
GUID-AB08BEE6-3A7D-4101-A2AE-29A633EB14D3-low.gif
Figure 6-11 FLT OTP Thresholds vs. Junction Temperature
GUID-A3A705F8-2395-4CCC-B667-601FA3570281-low.gif
A.
Figure 6-13 Max. XCD Discharge Current vs. Junction Temperature
GUID-520EEA58-9028-42E3-AC0A-A4238C0BAEF2-low.gif
Figure 6-2 VDD Bias-Supply Current vs. Temperature
GUID-ECBFEC36-1BEA-410E-83A2-2AA324DF6418-low.gif
Figure 6-4 Percentage Variation of Maximum and Minimum CS Thresholds vs. Temperature
GUID-DC8E0C7A-3E1E-4E77-8D5A-0464BDF12019-low.gif
A.
Figure 6-6 CS Peak-Power Threshold for VVS < VVSLV(LR) vs. VS Line-Sense Currents
GUID-91FB845F-DD79-49B8-B62D-85B45C08B100-low.gif
Figure 6-8 VS Over-Voltage Threshold vs. Temperature
GUID-CCE0E1EF-1608-4ADD-A599-AFA5FC00CD60-low.gif
Figure 6-10 P13 Voltage vs. Temperature
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Figure 6-12 XCD Thresholds vs. Junction Temperature