The UCC28910 and UCC28911 are high-voltage flyback switchers that provide output voltage and current regulation without the use of an optical coupler. Both devices incorporate a 700-V power FET and a controller that process operating information from the flyback auxiliary winding and power FET to provide a precise output voltage and current control. The integrated high-voltage current source for startup that is switched off during device operation, and the controller current consumption is dynamically adjusted with load. Both enable the very low stand-by power consumption.
Control algorithms in the UCC28910 and UCC28911, combining switching frequency and peak primary current modulation, allow operating efficiencies to meet or exceed applicable standards. Discontinuous conduction mode (DCM) with valley switching is used to reduce switching losses. Built-in protection features help to keep secondary and primary component stress levels in check across the operating range. The frequency jitter helps to reduce EMI filter cost.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
UCC28910 | SOIC-7 (7) | 5.00 mm x 6.20 mm |
UCC28911 | SOIC-7 (7) | 5.00 mm x 6.20 mm |
Changes from C Revision (March 2015) to D Revision
Changes from August 2014 Revision (B) to C Revision
Changes from A Revision (July 2013) to B Revision
Changes from * Revision (July 2013) to A Revision
PIN | I/O(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
DRAIN | 8 | P | DRAIN, the drain of the internal power FET, but also the input for the high-voltage current source used to start up the device. |
GND | 1 | G | The ground pins (GND) are both the reference pins for the controller and the low-side return for the drive output. Special care should be taken to return all AC decoupling as close as possible to this pin and avoid any common trace length with analog signal return paths. |
2 | |||
3 | |||
IPK | 4 | O | IPK is used to set the maximum peak current flowing in the power FET that is proportional to the maximum output current. |
N/A | 7 | N/A | This pin is not present to provide enough distance between high voltage pin (DRAIN) and VDD pins. |
VDD | 6 | P | VDD is the supply pin to the controller. A carefully placed bypass capacitor to GND is required on this pin. |
VS | 5 | I | Voltage Sense (VS) is used to provide voltage and timing feedback to the controller. Normally this pin is connected to a voltage divider between an auxiliary winding and ground. The value of the upper resistor of this divider is used to program low line thresholds. |
The VDD pin is connected to a bypass capacitor to ground and typically to a rectifier diode connected to the auxiliary winding. The VDD turn on UVLO threshold is 9.5 V (VDDON typical) and turn off UVLO threshold is 6.5 V (VDDOFF typical). The pin is provided with an internal clamp that prevents the voltage from exceeding the absolute maximum rating of the pin. The internal clamp cannot absorb currents higher than 10 mA (see IVDD(clp) in Absolute Maximum Ratings). To avoid damaging the device, when the clamp flowing current exceeds 6 mA (IDDCLP_OC typical) the device stops switching. The VDD pin operating range is then from 7 V (VDDOFF maximum) up to 26 V (VDDCLAMP minimum). The USB charging specification requires that the output current operates in constant current mode from 5 V to a minimum of 2 V; this is easily achieved with a nominal VDD of approximately 17 V. Set NAS (auxiliary-to-secondary windings turn ratio) to 17 V / (VOUT + VF) where VF is the voltage drop on the output diode at low current. The additional VDD headroom up to the clamp allows for VDD to rise due to the leakage energy delivered to the VDD in high-load conditions.
The current consumption of the device depends upon the operating condition. The graph below shows the current consumption as a function of normalized converter output power.
The device is provided with three pins, shorted together, that are used as external ground reference to the controller for analog signal reference. The three pins also function to pull out the heat caused by the power dissipation of the internal power FET. Place the VDD bypass capacitor close to GND and VDD with short traces to minimize noise on the VS and IPK signal pins.
The VS pin is connected to a resistor divider from the auxiliary winding to ground. The VS input provides three functions.
The data provided in 1. and 2. are sensed during the MOSFET off-time; 3. is performed during the MOSFET on-time when the auxiliary-winding voltage is negative.
Connected between VS pin and the auxiliary winding there is the resistance RS1. During MOSFET on-time the auxiliary voltage is negative and proportional to the converter input voltage. The voltage on VS pin is clamped to GND and through the resistance RS1. During the on-time, the current sourced from the VS pin, proportional to converter input voltage and inversely proportional to resistance RS1, is sensed by the device. For the under-voltage function, the enable threshold on VS current is 210 μA and the disable threshold is 75 μA.
The resistor values for RS1 and RS2 can be determined by the equations below.
where
where
A resistance (RIPK) connected between IPK pin and GND sets the maximum value of the power FET peak current, ID_PK(max). A current, ISENSE, proportional to the power FET current, comes out from the IPK pin during power FET on time. The voltage across RIPK is fed to the PWM comparator and establish to switch off the power FET according to the following equation:
where
If the IPK pin is shorted to GND (RIPK = 0), the peak current is automatically set to ID_PEAK(max), 600 mA for UCC28910, or 700 mA for UCC28911.
A test is performed at device start up to check whether the IPK pin is shorted to GND or the RIPK is present. If RIPK is less than RIPK_SHORT (maximum), the device interprets it as a short (RIPK = 0) and the DRAIN peak current is set to ID_PEAK(max). Otherwise, if RIPK is greater than RIPK(min) (minimum), the device sets the peak current DRAIN according to the previous equation. A value of RIPK that is in between the before said values is not allowed since the value of the peak current may be selected using either of the two sense resistances: the internal sense resistance and RIPK.
The DRAIN pin is connected to the DRAIN of the internal power FET. This pin also provides current to the high voltage current source at start up.