JAJSDH4I June   2017  – March 2024 UCC5310 , UCC5320 , UCC5350 , UCC5390

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Function
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications for D Package
    7. 6.7  Insulation Specifications for DWV Package
    8. 6.8  Safety-Related Certifications For D Package
    9. 6.9  Safety-Related Certifications For DWV Package
    10. 6.10 Safety Limiting Values
    11. 6.11 Electrical Characteristics
    12. 6.12 Switching Characteristics
    13. 6.13 Insulation Characteristics Curves
    14. 6.14 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Propagation Delay, Inverting, and Noninverting Configuration
      1. 7.1.1 CMTI Testing
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Supply
      2. 8.3.2 Input Stage
      3. 8.3.3 Output Stage
      4. 8.3.4 Protection Features
        1. 8.3.4.1 Undervoltage Lockout (UVLO)
        2. 8.3.4.2 Active Pulldown
        3. 8.3.4.3 Short-Circuit Clamping
        4. 8.3.4.4 Active Miller Clamp (UCC53x0M)
    4. 8.4 Device Functional Modes
      1. 8.4.1 ESD Structure
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Designing IN+ and IN– Input Filter
        2. 9.2.2.2 Gate-Driver Output Resistor
        3. 9.2.2.3 Estimate Gate-Driver Power Loss
        4. 9.2.2.4 Estimating Junction Temperature
      3. 9.2.3 Selecting VCC1 and VCC2 Capacitors
        1. 9.2.3.1 Selecting a VCC1 Capacitor
        2. 9.2.3.2 Selecting a VCC2 Capacitor
        3. 9.2.3.3 Application Circuits with Output Stage Negative Bias
      4. 9.2.4 Application Curve
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 PCB Material
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 サード・パーティ製品に関する免責事項
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Certifications
    4. 12.4 ドキュメントの更新通知を受け取る方法
    5. 12.5 サポート・リソース
    6. 12.6 Trademarks
    7. 12.7 静電気放電に関する注意事項
    8. 12.8 用語集
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.4.1 Undervoltage Lockout (UVLO)

UVLO functions are implemented for both the VCC1 and VCC2 supplies between the VCC1 and GND1, and VCC2 and VEE2 pins to prevent an underdriven condition on IGBTs and MOSFETs. When VCC is lower than VIT+ (UVLO) at device start-up or lower than VIT–(UVLO) after start-up, the voltage-supply UVLO feature holds the effected output low, regardless of the input pins (IN+ and IN–) as shown in Table 8-2. The VCC UVLO protection has a hysteresis feature (Vhys(UVLO)). This hysteresis prevents chatter when the power supply produces ground noise; this allows the device to permit small drops in bias voltage, which occurs when the device starts switching and operating current consumption increases suddenly. Figure 8-9 shows the UVLO functions.

Table 8-2 UCC53x0 VCC1 UVLO Logic
CONDITION INPUTS OUTPUTS
IN+ IN– OUTH OUT, OUTL
VCC1 – GND1 < VIT+(UVLO1) during device start-up H L Hi-Z L
L H Hi-Z L
H H Hi-Z L
L L Hi-Z L
VCC1 – GND1 < VIT–(UVLO1) after device start-up H L Hi-Z L
L H Hi-Z L
H H Hi-Z L
L L Hi-Z L
Table 8-3 UCC53x0 VCC2 UVLO Logic
CONDITION INPUTS OUTPUTS
IN+ IN– OUTH OUT, OUTL
VCC2 – VEE2 < VIT+(UVLO2) during device start-up H L Hi-Z L
L H Hi-Z L
H H Hi-Z L
L L Hi-Z L
VCC2 – VEE2 < VIT–(UVLO2) after device start-up H L Hi-Z L
L H Hi-Z L
H H Hi-Z L
L L Hi-Z L

When VCC1 or VCC2 drops below the UVLO1 or UVLO2 threshold, a delay, tUVLO1_rec or tUVLO2_rec, occurs on the output when the supply voltage rises above VIT+(UVLO) or VIT+(UVLO2) again. Figure 8-9 shows this delay.

GUID-321290E4-9770-41D2-864E-2E6E36B6C4CD-low.gif Figure 8-9 UVLO Functions