JAJSI61B June   2019  – February 2024 UCC5390-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Function
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications for DWV Package
    7. 5.7  Safety-Related Certifications For DWV Package
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics
    10. 5.10 Switching Characteristics
    11. 5.11 Insulation Characteristics Curves
    12. 5.12 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Propagation Delay, Inverting, and Noninverting Configuration
      1. 6.1.1 CMTI Testing
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Supply
      2. 7.3.2 Input Stage
      3. 7.3.3 Output Stage
      4. 7.3.4 Protection Features
        1. 7.3.4.1 Undervoltage Lockout (UVLO)
        2. 7.3.4.2 Active Pulldown
        3. 7.3.4.3 Short-Circuit Clamping
    4. 7.4 Device Functional Modes
      1. 7.4.1 ESD Structure
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Designing IN+ and IN– Input Filter
        2. 8.2.2.2 Gate-Driver Output Resistor
        3. 8.2.2.3 Estimate Gate-Driver Power Loss
        4. 8.2.2.4 Estimating Junction Temperature
      3. 8.2.3 Selecting VCC1 and VCC2 Capacitors
        1. 8.2.3.1 Selecting a VCC1 Capacitor
        2. 8.2.3.2 Selecting a VCC2 Capacitor
        3. 8.2.3.3 Application Circuits With Output Stage Negative Bias
      4. 8.2.4 Application Curve
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 PCB Material
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 サード・パーティ製品に関する免責事項
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Certifications
    4. 11.4 ドキュメントの更新通知を受け取る方法
    5. 11.5 サポート・リソース
    6. 11.6 Trademarks
    7. 11.7 静電気放電に関する注意事項
    8. 11.8 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.2.3 Estimate Gate-Driver Power Loss

The total loss, PG, in the gate-driver subsystem includes the power losses (PGD) of the UCC5390-Q1 device and the power losses in the peripheral circuitry, such as the external gate-drive resistor.

The PGD value is the key power loss which determines the thermal safety-related limits of the UCC5390-Q1 device, and it can be estimated by calculating losses from several components.

The first component is the static power loss, PGDQ, which includes quiescent power loss on the driver as well as driver self-power consumption when operating with a certain switching frequency. The PGDQ parameter is measured on the bench with no load connected to the OUT pins at a given VCC1, VCC2, switching frequency, and ambient temperature. In this example, VCC1 is 3.3V, VCC2 is 18 V and VEE2 is -3 V. The current on each power supply, with PWM switching from 0 V to 3.3 V at 300 kHz, is measured to be ICC1 = 1.67 mA and ICC2 = 1.28 mA. Therefore, use Equation 5 to calculate PGDQ.

Equation 5. GUID-B9140B7A-9901-46CA-981B-B83F0BE82EFE-low.gif

The second component is the switching operation loss, PGDO, with a given load capacitance which the driver charges and discharges the load during each switching cycle. Use Equation 6 to calculate the total dynamic loss from load switching, PGSW.

Equation 6. GUID-7FD73D46-43A4-4F19-A527-9269775123EA-low.gif

where

  • QG is the gate charge of the power transistor at VCC2.

So, for this example application the total dynamic loss from load switching is approximately 793.8 mW as calculated in Equation 7.

Equation 7. GUID-903B4EA8-8452-4282-B530-F5793C4B62DD-low.gif

QG represents the total gate charge of the power transistor and is subject to change with different testing conditions. The UCC5390-Q1 gate-driver loss on the output stage, PGDO, is part of PGSW. PGDO is equal to PGSW if the external gate-driver resistance and power-transistor internal resistance are 0 Ω, and all the gate driver-loss will be dissipated inside the UCC5390-Q1. If an external turn-on and turn-off resistance exists, the total loss is distributed between the gate driver pull-up/down resistance, external gate resistance, and power-transistor internal resistance. Importantly, the pull-up/down resistance is a linear and fixed resistance if the source/sink current is not saturated to 17 A, however, it will be non-linear if the source/sink current is saturated. Therefore, PGDO is different in these two scenarios.

Case 1 - Linear Pull-Up/Down Resistor:

Equation 8. GUID-8A294118-7895-4F09-A427-D7DDAB0D407C-low.gif

In this design example, all the predicted source and sink currents are less than 17 A, therefore, use Equation 9 to estimate the UCC5390-Q1 gate-driver loss.

Equation 9. GUID-55B96D94-70D8-4489-AE4C-E99BA15493A8-low.gif


Case 2 - Nonlinear Pull-Up/Down Resistor:

Equation 10. GUID-0489D1E6-B61A-4A51-9905-DEFA1F0D9E85-low.gif

where

  • VOUTH/L(t) is the gate-driver OUT pin voltage during the turnon and turnoff period. In cases where the output is saturated for some time, this value can be simplified as a constant-current source (17 A at turnon and turnoff) charging or discharging a load capacitor. Then, the VOUTH/L(t) waveform will be linear and the TR_Sys and TF_Sys can be easily predicted.

For some scenarios, if only one of the pull-up or pull-down circuits is saturated and another one is not, the PGDO is a combination of case 1 and case 2, and the equations can be easily identified for the pull-up and pull-down based on this discussion.

Use Equation 11 to calculate the total gate-driver loss dissipated in the UCC5390-Q1 gate driver, PGD.

Equation 11. GUID-D372844D-200C-44DF-A2DF-2FC7253F96E7-low.gif