The UCD90240 is a 24-rail PMBus addressable power sequencer and system manager in a compact 9-mm × 9-mm BGA package.
The device provides 24 analog monitor (MON) pins to monitor power-supply voltage, current, or temperature with two 12-bit ADC engines, 24 dedicated enable (EN) pins to control power rail on/off, 24 dedicated margin pins for closed-loop margining, 12 Logic GPO (LGPO) pins to support flexible Boolean logic and state machine functions, and 24 GPIO pins which can be configured as GPI, GPO, System Reset, cascading fault pins, and Watchdog I/O, and so forth.
The 24 EN pins and the 12 LGPO pins can be configured to be active driven or open-drain outputs.
Nonvolatile Event Logging preserves fault events after power dropout. Black Box Fault Log feature preserves the status of all rails and I/O pins when the first fault occurs.
The cascading feature offers convenient ways to manage up to 96 voltage rails through one SYNC_CLK pin connection. The Fault Pin feature coordinates among cascaded devices to take synchronized fault responses.
The Pin-Selected Rail States feature uses up to three GPIs to control up to eight user-defined power states. These states can implement system low-power modes as outlined in the Advanced Configuration and Power Interface (ACPI) specification.
The TI Fusion Digital Power™ designer software is an intuitive PC-based graphical user interface (GUI) that can configure, store, and monitor all system operating parameters.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
UCD90240 | BGA (157) | 9.00 mm × 9.00 mm |
DATE | REVISION | NOTES |
---|---|---|
February 2015 | * | Initial release. |
PIN | I/O TYPE |
DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
ANALOG MONITOR PINS | |||
MON1 | E2 | I | Analog input monitor pin |
MON2 | E1 | I | Analog input monitor pin |
MON3 | F2 | I | Analog input monitor pin |
MON4 | F1 | I | Analog input monitor pin |
MON5 | B3 | I | Analog input monitor pin |
MON6 | A3 | I | Analog input monitor pin |
MON7 | B4 | I | Analog input monitor pin |
MON8 | A4 | I | Analog input monitor pin |
MON9 | B5 | I | Analog input monitor pin |
MON10 | A5 | I | Analog input monitor pin |
MON11 | B6 | I | Analog input monitor pin |
MON12 | A6 | I | Analog input monitor pin |
MON13 | C1 | I | Analog input monitor pin |
MON14 | C2 | I | Analog input monitor pin |
MON15 | B1 | I | Analog input monitor pin |
MON16 | B2 | I | Analog input monitor pin |
MON17 | G2 | I | Analog input monitor pin |
MON18 | G1 | I | Analog input monitor pin |
MON19 | H1 | I | Analog input monitor pin |
MON20 | H2 | I | Analog input monitor pin |
MON21 | B7 | I | Analog input monitor pin |
MON22 | A7 | I | Analog input monitor pin |
MON23 | B8 | I | Analog input monitor pin |
MON24 | A8 | I | Analog input monitor pin |
ENABLE PINS | |||
EN1 | M9 | O | Digital output, rail enable signal |
EN2 | N9 | O | Digital output, rail enable signal |
EN3 | L10 | O | Digital output, rail enable signal |
EN4 | K10 | O | Digital output, rail enable signal |
EN5 | L9 | O | Digital output, rail enable signal |
EN6 | K9 | O | Digital output, rail enable signal |
EN7 | N8 | O | Digital output, rail enable signal |
EN8 | M8 | O | Digital output, rail enable signal |
EN9 | L8 | O | Digital output, rail enable signal |
EN10 | K8 | O | Digital output, rail enable signal |
EN11 | N7 | O | Digital output, rail enable signal |
EN12 | M7 | O | Digital output, rail enable signal |
EN13 | K7 | O | Digital output, rail enable signal |
EN14 | L7 | O | Digital output, rail enable signal |
EN15 | N4 | O | Digital output, rail enable signal |
EN16 | N3 | O | Digital output, rail enable signal |
EN17 | K3 | O | Digital output, rail enable signal |
EN18 | K4 | O | Digital output, rail enable signal |
EN19 | J4 | O | Digital output, rail enable signal |
EN20 | J2 | O | Digital output, rail enable signal |
EN21 | J3 | O | Digital output, rail enable signal |
EN22 | H4 | O | Digital output, rail enable signal |
EN23 | H3 | O | Digital output, rail enable signal |
EN24 | G4 | O | Digital output, rail enable signal |
CLOSED-LOOP MARGIN PINS | |||
MARGIN1 | J13 | O | Closed-loop margin PWM output |
MARGIN2 | L5 | O | Closed-loop margin PWM output |
MARGIN3 | D8 | O | Closed-loop margin PWM output |
MARGIN4 | K6 | O | Closed-loop margin PWM output |
MARGIN5 | D4 | O | Closed-loop margin PWM output |
MARGIN6 | E4 | O | Closed-loop margin PWM output |
MARGIN7 | F5 | O | Closed-loop margin PWM output |
MARGIN8 | N5 | O | Closed-loop margin PWM output |
MARGIN9 | N6 | O | Closed-loop margin PWM output |
MARGIN10 | K5 | O | Closed-loop margin PWM output |
MARGIN11 | M6 | O | Closed-loop margin PWM output |
MARGIN12 | L6 | O | Closed-loop margin PWM output |
MARGIN13 | D11 | O | Closed-loop margin PWM output |
MARGIN14 | C12 | O | Closed-loop margin PWM output |
MARGIN15 | A13 | O | Closed-loop margin PWM output |
MARGIN16 | B13 | O | Closed-loop margin PWM output |
MARGIN17 | D12 | O | Closed-loop margin PWM output |
MARGIN18 | C13 | O | Closed-loop margin PWM output |
MARGIN19 | E12 | O | Closed-loop margin PWM output |
MARGIN20 | E13 | O | Closed-loop margin PWM output |
MARGIN21 | M13 | O | Closed-loop margin PWM output |
MARGIN22 | L12 | O | Closed-loop margin PWM output |
MARGIN23 | M5 | O | Closed-loop margin PWM output |
MARGIN24 | J12 | O | Closed-loop margin PWM output |
GPIO and CASCADING PINS | |||
GPIO1 | L4 | I/O | GPI / Command GPO / WDI / WDO / System Reset / Fault Pin for multiple chip cascading |
GPIO2 | N1 | I/O | GPI / Command GPO / WDI / WDO / System Reset / Fault Pin for multiple chip cascading |
GPIO3 | M4 | I/O | GPI / Command GPO / WDI / WDO / System Reset / Fault Pin for multiple chip cascading |
GPIO4 | N2 | I/O | GPI / Command GPO / WDI / WDO / System Reset / Fault Pin for multiple chip cascading |
GPIO5 | F4 | I/O | GPI / Command GPO / WDI / WDO / System Reset / Fault Pin for multiple chip cascading |
GPIO6 | F3 | I/O | GPI / Command GPO / WDI / WDO / System Reset / Fault Pin for multiple chip cascading |
GPIO7 | G3 | I/O | GPI / Command GPO / WDI / WDO / System Reset / Fault Pin for multiple chip cascading |
GPIO8 | D10 | I/O | GPI / Command GPO / WDI / WDO / System Reset / Fault Pin for multiple chip cascading |
GPIO9 | L11 | I/O | GPI / Command GPO / WDI / WDO / System Reset / Fault Pin for multiple chip cascading |
GPIO10 | N12 | I/O | GPI / Command GPO / WDI / WDO / System Reset / Fault Pin for multiple chip cascading |
GPIO11 | N11 | I/O | GPI / Command GPO / WDI / WDO / System Reset / Fault Pin for multiple chip cascading |
GPIO12 | M11 | I/O | GPI / Command GPO / WDI / WDO / System Reset / Fault Pin for multiple chip cascading |
GPIO13 | F13 | I/O | GPI / Command GPO / WDI / WDO / System Reset / Fault Pin for multiple chip cascading |
GPIO14 | F12 | I/O | GPI / Command GPO / WDI / WDO / System Reset / Fault Pin for multiple chip cascading |
GPIO15 | G11 | I/O | GPI / Command GPO / WDI / WDO / System Reset / Fault Pin for multiple chip cascading |
GPIO16 | H10 | I/O | GPI / Command GPO / WDI / WDO / System Reset / Fault Pin for multiple chip cascading |
GPIO17 | H13 | I/O | GPI / Command GPO / WDI / WDO / System Reset / Fault Pin for multiple chip cascading |
GPIO18 | H12 | I/O | GPI / Command GPO / WDI / WDO / System Reset / Fault Pin for multiple chip cascading |
GPIO19 | H11 | I/O | GPI / Command GPO / WDI / WDO / System Reset / Fault Pin for multiple chip cascading |
GPIO20 | L13 | I/O | GPI / Command GPO / WDI / WDO / System Reset / Fault Pin for multiple chip cascading |
GPIO21 | B11 | I/O | GPI / Command GPO / WDI / WDO / System Reset / Fault Pin for multiple chip cascading |
GPIO22 | B12 | I/O | GPI / Command GPO / WDI / WDO / System Reset / Fault Pin for multiple chip cascading |
GPIO23 | C11 | I/O | GPI / Command GPO / WDI / WDO / System Reset / Fault Pin for multiple chip cascading |
GPIO24 | A12 | I/O | GPI / Command GPO / WDI / WDO / System Reset / Fault Pin for multiple chip cascading |
SYNC_CLK | K2 | I/O | Synchronization clock I/O for multiple chip cascading |
Logic GPO PINS | |||
LGPO1 | C9 | O | Logic GPO |
LGPO2 | B9 | O | Logic GPO |
LGPO3 | A9 | O | Logic GPO |
LGPO4 | C8 | O | Logic GPO |
LGPO5 | D5 | O | Logic GPO |
LGPO6 | C5 | O | Logic GPO |
LGPO7 | C6 | O | Logic GPO |
LGPO8 | C4 | O | Logic GPO |
LGPO9 | L3 | O | Logic GPO |
LGPO10 | M1 | O | Logic GPO |
LGPO11 | M2 | O | Logic GPO |
LGPO12 | M3 | O | Logic GPO |
PMBus COMM INTERFACE | |||
PMBUS_CLK | E10 | I | PMBus clock (must pull up to V33D) |
PMBUS_DATA | D13 | I/O | PMBus data (must pull up to V33D) |
PMBALERT# | F11 | O | PMBus alert, active-low, open-drain output (must pull up to V33D) |
PMBUS_CNTRL | E11 | I | PMBus control pin |
PMBUS_ADDR0 | L2 | I | PMBus digital address input. Bit 0. |
PMBUS_ADDR1 | L1 | I | PMBus digital address input. Bit 1. |
PMBUS_ADDR2 | K1 | I | PMBus digital address input. Bit 2. |
JTAG | |||
JTAG_TMS | A10 | I | Test mode select with internal pullup |
JTAG_TCK | C10 | I | Test clock with internal pullup |
JTAG_TDO | A11 | I/O | Test data out with internal pullup |
JTAG_TDI | B10 | I/O | Test data in with internal pullup |
INPUT POWER, GROUND, AND EXTERNAL REFERENCE PINS | |||
RESET | G10 | I | Active-low device reset input. Pull up to V33D. |
V33A | D3 | I | Analog 3.3-V supply. It should be decoupled from V33D to minimize the electrical noise contained on V33D from affecting the analog functions. |
V33D | D7 E6 E8 E9 F10 J7 J9 J10 |
I | Digital 3.3-V supply for I/O and some logic. |
BPCap | D6 J1 J6 K13 |
I | Positive supply for most of the logic function, including the processor core and most peripherals. The voltage on this pin is 1.2 V and is supplied by the on-chip LDO. The BPCap pins should only be connected to each other and an external capacitor as specified in On-Chip Low Drop-Out (LDO) Regulator Characteristics section. |
AVSS | C3 E3 |
I | Analog ground. These are separated from DVSS to minimize the electrical noise contained on V33D from affecting the analog functions. |
DVSS | A1 C7 D9 E5 F9 H5 H9 J5 J8 J11 |
I | Ground reference for logic and I/O pins. |
VREFA+ | D2 | I | (Optional) Positive node of external reference voltage |
VREFA- | D1 | I | (Optional) Negative node of external reference voltage |
UNUSED PINS | |||
UNUSED-NC | A2 G13 M12 N10 |
Do not connect. Leave floating/isolated. | |
UNUSED-DVSS | G12 K11 M10 N13 |
Tie to DVSS. | |
UNUSED-V33D | K12 | Tie to V33D. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Voltage applied at V33D to DVSS | 0 | 4 | V | |
Voltage applied at V33A to AVSS | 0 | 4 | V | |
Input voltage on all I/O pins except PMBUS_CNTRL, PMBALERT#, MARGIN19 and MARGIN20, regardless of whether the device is powered(2)(3) | –0.3 | 5.5 | V | |
Input voltage on PMBUS_CNTRL, PMBALERT#, MARGIN19 and MARGIN20 | –0.3 | V33D+0.3 | V | |
Maximum current per output pin | – | 25 | mA | |
Maximum junction temperature | – | 150 | °C | |
Unpowered storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
V33D supply voltage | 3.15 | 3.3 | 3.63 | V | |
V33A supply voltage(1) | 2.97 | 3.3 | 3.63 | V | |
TA | Ambient operating temperature range | –40 | – | +85 | °C |
TC | Case operating temperature range | –40 | – | +90 | °C |
TJ | Junction operating temperature range | –40 | – | +93 | °C |
THERMAL METRIC(1) | UCD90240 | UNIT | |
---|---|---|---|
BGA | |||
157 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 41.6 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 15.8 | |
RθJB | Junction-to-board thermal resistance | 18.9 | |
ψJT | Junction-to-top characterization parameter | 0.3 | |
ψJB | Junction-to-board characterization parameter | 20.3 | |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | ||
TJ | Junction temperature formula | TC + (P × ΨJT) TPCB +(P × ΨJB)(2) TA + (P × ΘJA)(3) TB + (P × ΘJB)(4)(5) |
°C |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SUPPLY CURRENT | ||||||
IV33 | Supply current | V33D = V33A = 3.3V | – | 31.4 | 54.9 | mA |
ON-CHIP LOW DROP-OUT (LDO) REGULATOR | ||||||
CLDO | External filter capacitor size for internal power supply(1) | 2.5 | – | 4.0 | µF | |
ESR | Filter capacitor equivalent series resistance | 10 | – | 100 | mΩ | |
ESL | Filter capacitor equivalent series inductance | – | – | 0.5 | nH | |
VLDO | LDO output voltage | 1.08 | 1.2 | 1.32 | V | |
IINRUSH | Inrush current | 50 | – | 250 | mA | |
ANALOG-TO-DIGITAL CONVERTER (ADC)(2) | ||||||
V33A | ADC supply voltage | 2.97 | 3.3 | 3.63 | V | |
AVSS | ADC ground voltage | – | 0 | – | V | |
CV33A | Voltage reference decoupling capacitance between V33A and AVSS | – | 1.0/0.01(4) | – | ||
VREFA+ | Positive external voltage reference on VREFA+ pin | 2.4 | – | 3 | V | |
VREFA– | Negative external voltage reference on VREFA– pin | AVSS | AVSS | 0.3 | V | |
CREF | Voltage reference decoupling capacitance between VREFA+ and VREFA– (if using external reference) | – | 1.0/0.01(4) | – | µF | |
VADCIN | Analog input range, internal reference(5) | 0 | – | V33A | V | |
Analog input range, external reference(6) | VREFA– | – | VREFA+ | |||
IL | ADC input leakage current | – | – | 2.0 | µA | |
RADC | ADC equivalent input resistance | 2.5 | kΩ | |||
CADC | ADC equivalent input capacitance | 10 | pF | |||
FCONV | ADC conversion rate (on each ADC channel)(2) | 1 | MSPS | |||
N | ADC resolution | 12 | bits | |||
ET | Total unadjusted error, over full input range when using internal reference(3) | ±10 | ±30 | LSB | ||
Total unadjusted error, over full input range when using external reference(3) | ±2.5 | ±4.0 | ||||
DIGITAL INPUTS AND OUTPUTS (GPIO, LOGIC GPO, EN, AND MARGIN PINS) | ||||||
VIH | I/O high-level input voltage(7) | 0.65×V33D | – | 5.5V | V | |
VIL | I/O low-level input voltage | 0 | – | 0.35×V33D | V | |
VHYS | I/O input hysteresis | 0.2 | – | – | V | |
VOH | I/O high-level output voltage | 2.4 | – | – | V | |
VOL | I/O low-level output voltage | – | – | 0.4 | V | |
IOH | High-level source current, VOH = 2.4V(8) | 4.0 | – | – | mA | |
IOL | Low-level sink current, VOL = 0.4V(8) | 4.0 | – | – | mA | |
RESET AND BROWNOUT | ||||||
V33DSlew | Minimum V33D slew rate between 2.8V and 3.2V | 0.1 | – | – | V/ms | |
VRESET | Supply voltage at which device comes out of reset | 2.85 | 3.00 | 3.15 | V | |
VBOR | Supply voltage at which device enters brownout | 2.93 | 3.02 | 3.11 | V | |
VSHDN | Supply voltage at which device shuts down | 2.70 | 2.78 | 2.87 | V | |
tRESET | Minimum low-pulse width needed at RESET pin | – | 250 | – | ns | |
tIRT | Internal Reset Time(9) | – | 9 | 11.5 | ms |
PARAMETER | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|
CONFIGURATION FLASH MEMORY | |||||
PECYC | Number of program/erase cycles before failure | 100 000 | – | – | Cycles |
TRET | Data retention, -40°C to +85°C | 20 | – | – | Years |
FAULT AND EVENT LOGGING EEPROM | |||||
EPECYC | Number of mass program/erase cycles of a single word before failure | 500 000 | – | – | Cycles |
ETRET | Data retention, -40°C to +85°C | 20 | – | – | Years |
PARAMETER | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|
I1 | t(HD:STA) | Start condition hold time | 450 | – | – | ns |
I2 | t(LOW) | Clock Low period(1) | 450 | – | – | ns |
I3 | tr | Clock/Data rise time(2) | – | – | See (2) | ns |
I4 | t(HD:DAT) | Data hold time | – | 25 | – | ns |
I5 | tf | Clock/Data fall time(3) | – | 112.5 | 125 | ns |
I6 | t(HIGH) | Clock High time | 300 | – | – | ns |
I7 | t(SU:DAT) | Data setup time | 225 | – | – | ns |
I8 | t(SU:STA) | Start condition setup time (Repeated start only) | 450 | – | – | ns |
I9 | t(SU:STO) | Stop condition setup time | 300 | – | – | ns |
I10 | t(DV) | Data Valid | – | 25 | – | ns |