JAJSCI5B august 2016 – march 2022 UCD9090A
PRODUCTION DATA
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
The number of configurable rails is a maximum of ten. The maximum number of configurable GPIs is eight. The maximum number of configurable boolean logic GPOs is ten.
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
ANALOG MONITOR INPUTS | |||
MON1 | 1 | I | Analog input (0 V–2.5 V) |
MON2 | 2 | I | Analog input (0 V–2.5 V) |
MON3 | 38 | I | Analog input (0 V–2.5 V) |
MON4 | 39 | I | Analog input (0 V–2.5 V) |
MON5 | 40 | I | Analog input (0 V–2.5 V) |
MON6 | 41 | I | Analog input (0 V–2.5 V) |
MON7 | 42 | I | Analog input (0 V–2.5 V) |
MON8 | 45 | I | Analog input (0 V–2.5 V) |
MON9 | 46 | I | Analog input (0 V–2.5 V) |
MON10 | 48 | I | Analog input (0 V–2.5 V) |
MON11 | 37 | I | Analog input (0.2 V–2.5 V) |
GPIO | |||
GPIO1 | 4 | I/O | General-purpose discrete I/O |
GPIO2 | 5 | I/O | General-purpose discrete I/O |
GPIO3 | 6 | I/O | General-purpose discrete I/O |
GPIO4 | 7 | I/O | General-purpose discrete I/O |
GPIO13 | 18 | I/O | General-purpose discrete I/O |
GPIO14 | 21 | I/O | General-purpose discrete I/O |
GPIO15 | 24 | I/O | General-purpose discrete I/O |
GPIO16 | 25 | I/O | General-purpose discrete I/O |
GPIO17 | 26 | I/O | General-purpose discrete I/O |
PWM OUTPUTS | |||
FPWM1/GPIO5 | 10 | I/O/PWM | PWM (15.259 kHz to 125 MHz) or GPIO |
FPWM2/GPIO6 | 11 | I/O/PWM | PWM (15.259 kHz to 125 MHz) or GPIO |
FPWM3/GPIO7 | 12 | I/O/PWM | PWM (15.259 kHz to 125 MHz) or GPIO |
FPWM4/GPIO8 | 13 | I/O/PWM | PWM (15.259 kHz to 125 MHz) or GPIO |
FPWM5/GPIO9 | 14 | I/O/PWM | PWM (15.259 kHz to 125 MHz) or GPIO |
FPWM6/GPIO10 | 15 | I/O/PWM | PWM (15.259 kHz to 125 MHz) or GPIO |
FPWM7/GPIO11 | 16 | I/O/PWM | PWM (15.259 kHz to 125 MHz) or GPIO |
FPWM8/GPIO12 | 17 | I/O/PWM | PWM (15.259 kHz to 125 MHz) or GPIO |
PWM1/GPI1 | 22 | I/PWM | PWM (0.93 Hz to 7.8125 MHz) or GPI |
PWM2/GPI2 | 23 | I/PWM | PWM (0.93 Hz to 7.8125 MHz) or GPI |
PMBus COMM INTERFACE | |||
PMBus_CLK | 8 | I/O | PMBus clock (must have pullup to 3.3 V) |
PMBus_DATA | 9 | I/O | PMBus data (must have pullup to 3.3 V) |
PMBus_ALERT | 19 | O | PMBus alert, active-low, open-drain output (must have pullup to 3.3 V) |
PMBus_CNTRL | 20 | I | PMBus control |
PMBus_ADDR0 | 44 | I | PMBus analog address input. Least-significant address bit |
PMBus_ADDR1 | 43 | I | PMBus analog address input. Most-significant address bit |
JTAG | |||
TCK/GPIO18 | 27 | I/O | Test clock or GPIO |
TDO/GPIO19 | 28 | I/O | Test data out or GPIO |
TDI/GPIO20 | 29 | I/O | Test data in (tie to Vdd with 10-kΩ resistor) or GPIO |
TMS/GPIO21 | 30 | I/O | Test mode select (tie to Vdd with 10-kΩ resistor) or GPIO |
TRST | 31 | I | Test reset – tie to ground with 10-kΩ resistor |
INPUT POWER AND GROUNDS | |||
RESET | 3 | — | Active-low device reset input. Hold low for at least 2 μs to reset the device. |
V33A | 34 | — | Analog 3.3-V supply. Refer to the Section 10.1 section. |
V33D | 33 | — | Digital core 3.3-V supply. Refer to the Section 10.1 section. |
BPCap | 35 | — | 1.8-V bypass capacitor. Refer to the Section 10.1 section. |
AVSS1 | 36 | — | Analog ground |
AVSS2 | 47 | — | Analog ground |
DVSS | 32 | — | Digital ground |
Thermal pad | — | QFN ground pad. Tie to ground plane. |