JAJSHP9E November   2007  – July 2019 VCA824

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      差動イコライザ
      2.      RC 負荷の差動イコライゼーション
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: VS = ±5 V
    6. 7.6 Typical Characteristics: VS = ±5 V, AVMAX = 2 V/V
    7. 7.7 Typical Characteristics: VS = ±5 V, AVMAX = 10 V/V
    8. 7.8 Typical Characteristics: VS = ±5 V, AVMAX = 40 V/V
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 Maximum Gain Of Operation
      2. 8.4.2 Output Current And Voltage
      3. 8.4.3 Input Voltage Dynamic Range
      4. 8.4.4 Output Voltage Dynamic Range
      5. 8.4.5 Bandwidth
      6. 8.4.6 Offset Adjustment
      7. 8.4.7 Noise
      8. 8.4.8 Input and ESD Protection
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Difference Amplifier
      2. 9.1.2 Differential Equalizer
      3. 9.1.3 Differential Cable Equalizer
      4. 9.1.4 Voltage-Controlled Lowpass Filter [application sub]
      5. 9.1.5 Wideband Variable Gain Amplifier Operation
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Thermal Considerations
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 開発サポート
        1. 12.1.1.1 デモ用基板
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.1.4 Voltage-Controlled Lowpass Filter [application sub]

In the circuit of Figure 74, the VCA824 serves as the variable-gain element of a voltage-controlled low-pass filter. This section discusses how this implementation expands the circuit voltage swing capability over that normally achieved with the equivalent multiplier implementation. The circuit control voltage, VG, is calculated as according to the simplified relationship described in Equation 6.

Equation 6. VCA824 q_vo_vi_bos394.gif
VCA824 ai_lo_pass_filt_bos394.gifFigure 74. Voltage-Control Low-Pass Filter

The response control results from amplification of the feedback voltage applied to R2. First, consider the case where the VCA824 produces G = 1V/V. Then this circuit performs as if the amplifier were replaced by a short circuit. Visually replacing the amplifier by a short leaves a simple voltage-feedback amplifier with a feedback resistor bypassed by a capacitor. Replacing this gain with a variable gain, G, the pole can be written as shown in Equation 7.

Equation 7. VCA824 q_f8_bos394.gif

Because the VCA824 is most linear in the midrange, the median of the adjustable pole should be set at VG = 0V (see Figure 13, Figure 33, Figure 54, and Equation 8). Selecting R1 = R2 = 332Ω, and targeting a median frequency of 10MHz, the capacitance (C) is 24pF. Because the OPA690 was selected for the circuit of Figure 74, and in order to limit peaking in the OPA690 frequency response, a capacitor equal to C was added on the inverting mode to ground. This architecture has the effect of setting the high-frequency noise gain of the OPA690 to 2V/V, ensuring stability and providing flat frequency response.

Equation 8. VCA824 q_n0p8v_bos394.gif

Once the median frequency is set, the maximum and minimum frequencies can be determined by using VG = –0.8 V and VG = 0.8 V in the gain equation of Equation 9. Note that this is a first-order analysis and does not take into consideration the open-loop gain limitation of the OPA690.

Equation 9. VCA824 q_g_2rf_rg_bos394.gif

With the components shown, the circuit provides a linear variation of the low-pass cutoff from 2MHz to 20MHz, using –1V ≤ VG ≤ 1V.