SLES275A January 2015 – December 2017 VSP5324-Q1
PRODUCTION DATA.
The VSP5324-Q1 device is a high-performance, 12-bit, quad-channel, analog-to-digital converter (ADC) with sample rates up to 80 MSPS. The conversion process is initiated by a rising edge of the external input clock and when the analog input signal is sampled. The sampled signal is sequentially converted by a series of small resolution stages, with the outputs combined in a digital correction logic block. At every clock edge the sample propagates through the pipeline, resulting in a data latency of 11 clock cycles. The output is available as 12-bit data, in serial (low-voltage differential signaling) LVDS format, coded in either offset binary or binary twos complement format.
The analog input consists of a switched-capacitor-based differential sample-and-hold architecture, as shown in Figure 42. This differential topology results in very good AC performance even for high-input frequencies at high sampling rates. The INx_P and INx_M pins must be externally biased around a common-mode voltage of 0.95 V, available on the VCM pin. For a full-scale differential input, each input pin (INx_P, INx_M) must swing symmetrically between VCM + 0.5 V and VCM – 0.5 V, resulting in a 2-VPP differential input swing. The input sampling circuit has a high 3-dB bandwidth that extends up to 550 MHz (measured from the input pins to the sampled voltage).
The analog input circuit small-signal bandwidth is high, approximately 550 MHz. When using an amplifier to drive the VSP5324-Q1 device, the total amplifier noise up to small-signal bandwidth must be considered. The device large-signal bandwidth depends on the input signal amplitude. The VSP5324-Q1 device supports 2-VPP amplitude for input signal frequencies up to 80 MHz. For higher frequencies (greater than 80 MHz), the input signal amplitude must be decreased proportionally. For example, at 160 MHz, the device supports a maximum of 1-VPP signal.
The VSP5324-Q1 device integrates a set of commonly-used digital functions that can be used to ease system design such as test patterns and gain.
The VSP5324-Q1 device includes programmable digital gain settings from 0 dB to 12 dB in 1-dB steps. The benefit of digital gain is to obtain improved SFDR performance. SFDR improvement is achieved at the expense of SNR; for each gain setting, SNR degrades by approximately 1 dB. Therefore, gain can be used to trade-off between SFDR and SNR.
For each gain setting, the analog input full-scale range support scales proportionally, as shown in Table 1. After reset, the device is in 0-dB gain mode. To use other gain settings, program the GAIN_CHx bits in registers 2Ah (see the Register 2Ah (offset = 2Ah) [reset = 0] section) and 2Bh (see the Register 2Bh (offset = 2Bh) [reset = 0] section).
DIGITAL GAIN (dB) | FULL-SCALE (VPP) |
---|---|
0 | 2 |
1 | 1.78 |
2 | 1.59 |
3 | 1.42 |
4 | 1.26 |
5 | 1.12 |
6 | 1.00 |
7 | 0.89 |
8 | 0.80 |
9 | 0.71 |
10 | 0.63 |
11 | 0.56 |
12 | 0.50 |
Normally, the INx_P pin represents the positive analog input pin and INx_M represents the complementary negative input. Setting the INVERT_ CH[4:1] bits listed in Table 2 (which provide individual control for each channel) causes the inputs to be swapped. INN now represents the positive input and INx_P represents the negative input.
ADDRESS (HEX) | D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
24 | PRBS_SEED[22:16] | X(1) | INVERT_CH4 | X | INVERT_CH3 | X | X | INVERT_CH2 | X | INVERT_CH1 |
The SYNC function can be used to synchronize the RAMP test patterns across channels. This function can be enabled using either the hardware pin (SYNC) or software register bits.
To enable the software sync, set the register bit, EN_SYNC. To use the SYNC pin, set the EN_SYNC and HARD_SYNC_TP register bits. Note that SYNC pin is disabled after reset.
Two output data formats are supported: twos complement and offset binary. These modes can be selected using the BTC_MODE serial interface register bit.
For a positive overload, the D[11:0] output data bits are FFFh in offset binary output format and 7FFh in twos complement output format. For a negative input overload, the output code is 000h in offset binary output format and 800h in twos complement output format.
The VSP5324-Q1 device offers several flexible output options which makes interfacing to an (application-specific integrated circuit) ASIC or an (field-programmable gate array) FPGA easy. Each option can be easily programmed using the serial interface. Table 3 lists a summary of all options. This table also lists the default values after power-up and reset and a detailed description of each option. The output interface options are one-lane and two-lane serialization, and are described in the One-Lane, 12x Serialization with DDR Bit Clock and 1x Frame Clock and Two-Lane, 6x Serialization with DDR Bit Clock and 0.5x Frame Clock sections, respectively.
FEATURE | OPTIONS | AVAILABLE IN | DEFAULT AFTER RESET | DESCRIPTION | |
---|---|---|---|---|---|
ONE-LANE | TWO-LANE | ||||
Lane interface | One and two lanes | Yes | Yes | One-lane | One-lane: ADC data are sent serially over one pair of LVDS pins Two-lane: ADC data are split and sent serially over two pairs of LVDS pins |
Serialization factor | 12x | Yes | No | 12x | — |
DDR bit clock frequency | 6x | Yes | No | 6x | — |
3x | No | Yes | — | Only with two-lane interface | |
Frame clock frequency | 1x sample rate | Yes | No | 1x | — |
1/2x sample rate | No | Yes | — | Only with two-lane interface | |
Bit sequence | Byte-wise | No | Yes | Byte-wise | These options are available only with two-lane interface. Byte wise: ADC data are split into upper and lower bytes that are output on separate lanes. Bit wise: ADC data are split into even and odd bits that are output on separate lanes. Word wise: Successive ADC data samples are sent over separate lanes. |
Bit-wise | No | Yes | Byte-wise | ||
Word-wise | No | Yes | Byte-wise |
The 12-bit ADC data are serialized and output over one LVDS pair per channel along with a 6x bit clock and 1x frame clock, as shown in Figure 43. The output data rate is 12x sample rate and is therefore suited for low sample rates (typically up to 50 MSPS).
NOINDENT:
Upper number is the data bit in MSB-first mode. Lower number in parenthesis is the data bit in LSB-first mode.In the two-lane serialization option, the 12-bit ADC data are serialized and output over two LVDS pairs per channel. The output data rate is a 6x sample rate with a 3x bit clock and a 1x frame clock.
Compared to the one-line scenario, the two-line output data rate is half the amount. This difference allows the device to be used up to the maximum sampling rate. Two-lane serialization is available in bit-, byte-, and word-wise modes. Figure 44 shows the bit- and byte-wise modes and Figure 45 shows the word-wise mode.
NOINDENT:
The upper number is the data bit in MSB-first mode. The lower number in parenthesis is the data bit in LSB-first mode.NOINDENT:
The unshaded cells indicate sample N data. The shaded cells indicate sample N + 1 data.NOINDENT:
The upper number is the data bit in MSB-first mode. The lower number in parenthesis is the data bit in LSB-first mode.NOINDENT:
The unshaded cells indicate sample N data. The shaded cells indicate sample N + 1 data.The VSP5324-Q1 output interface is normally a DDR interface with the LCLK rising and falling edge transitions in the middle of alternate data windows. Figure 46 shows this default phase.
The LCLK phase can be programmed relative to the output frame clock and data using the PHASE_DDR[1:0] bits in Table 4. Figure 47 shows the LCLK phase modes.
ADDRESS (HEX) | D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
42 | EN_REF_VCM0 | X(1) | X | X | X | X | X | X | X | PHASE_DDR[1:0] | X | EN_REF_VCM1 | X | X | X |
Figure 48 shows the equivalent circuit of each LVDS output buffer. After reset, the buffer presents a 100-Ω output impedance to match the external 100-Ω termination.
The VID voltage is nominally 350 mV, resulting in an output swing of ±350 mV with 100-Ω external termination. The buffer output impedance behaves in the same way as a source-side series termination. By absorbing reflections from the receiver end, the buffer helps improve signal integrity.
The VSP5324-Q1 device supports an external reference mode of operation either by:
This mode can be used to operate multiple VSP5324-Q1 chips with the same (externally applied) reference voltage.
For normal operation, the device requires two reference voltages, REFT and REFB. By default, the device generates these two voltages internally. To enable the external reference mode, set the register bits as listed in Table 5. This procedure powers down the internal reference amplifier and the two reference voltages can be forced directly on the REFT and REFB pins as (V(REFT) = 1.45 V ± 50 mV) and (V(REFB) = 0.45 V ±50 mV).
Use to calculate the relationship between the ADC full-scale input voltage (VFS) and the applied reference voltages.
In this mode, an external reference voltage (VREFIN) can be applied to the VCM pin. UseEquation 2 to calculate the relationship between the ADC full-scale input voltage and VREFIN.
To enable this mode, set the register bits as listed in Table 5. This action changes the function of the VCM pin to an external reference input pin. The voltage applied on VCM must be 1.5 V ±50 mV.
FUNCTION | EN_HIGH_ADDRS | EN_EXT_REF | EXT_REF_VCM |
---|---|---|---|
External reference using the REFT and REFB pins | 1 | 1 | 00 |
External reference using the VCM pin | 1 | 1 | 11 |
The VSP5324-Q1 device has a set of internal registers that can be accessed by the serial interface formed by the CS (serial interface enable), SCLK (serial interface clock), and SDATA (serial interface data) pins. When CS is low the following occurs:
If the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data can be loaded in multiples of 24-bit words within a single active CS pulse.
The first eight bits form the register address and the remaining 16 bits form the register data. The interface can function with SCLK frequencies from 15 MHz down to very low speeds (of few Hertz) and also with a non-50% SCLK duty cycle.
After power-up, the internal registers must be initialized to the default values. This reset can be accomplished in one of two ways:
See the Serial Interface Timing Requirements section and Figure 3 for timing information.
The device includes a mode where the contents of the internal registers can be readback on the SDOUT pin, as shown in Figure 49. This mode can useful as a diagnostic check to verify the serial interface communication between the external controller and ADC.
By default, after power-up and device reset, the SDOUT pin is high-impedance. When readout mode is enabled using the READOUT register bit, the SDOUT pin outputs the contents of the selected register serially in the following sequence:
After reset, the device default states include the following:
ADDRESS | D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
00 | X(1) | X | X | X | X | X | X | X | X | X | X | X | X | X | X | RST |
01 | X | X | X | X | X | X | X | X | X | X | X | EN_HIGH_ ADDRS |
X | X | X | READOUT |
02 | X | X | EN_SYNC | X | X | X | X | X | X | X | X | X | X | X | X | X |
0A | RAMP_PAT_RESET_VAL | |||||||||||||||
0F | X | X | X | X | X | PDN_PIN_ CFG |
PDN_ COM PLETE |
PDN_ PARTIAL |
PDN_CH4 | X | PDN_CH3 | X | PDN_CH2 | X | PDN_CH1 | X |
14 | X | X | X | X | X | X | X | X | LFNS_CH4 | X | LFNS_CH3 | X | X | LFNS_CH2 | X | LFNS_CH1 |
1C | X | EN_ FRAME_ PAT |
ADCLKOUT[11:0] | X | X | |||||||||||
23 | PRBS_SEED[15:0] | |||||||||||||||
24 | PRBS_SEED[22:16] | X | INVERT_ CH4 |
X | INVERT_ CH3 |
X | X | INVERT_ CH2 |
X | INVERT_ CH1 |
||||||
25 | HARD_ SYNC_TP |
PRBS_ SEED_ FROM_ REG |
X | PRBS_ TP_EN |
X | X | X | TP_SOFT_SYNC | X | EN_RAMP | DUAL_ CUSTOM_ PAT |
SINGLE_ CUSTOM_ PAT |
BITS_CUSTOM2[13:12] | BITS_CUSTOM1[13:12] | ||
26 | BITS_CUSTOM1[9:0] | X | X | X | X | X | X | |||||||||
27 | BITS_CUSTOM2[9:0] | X | X | X | X | X | X | |||||||||
28 | EN_BIT ORDER |
X | X | X | X | X | X | BIT_WISE | EN_WORDWISE_BY_CH[7:0] | |||||||
29 | X | X | X | X | X | X | X | X | X | X | X | X | X | X | GLOBAL_ EN_FILTER |
X |
2A | X | X | X | X | GAIN_CH2[3:0] | X | X | X | X | GAIN_CH1[3:0] | ||||||
2B | X | X | X | X | GAIN_CH3[3:0] | X | X | X | X | GAIN_CH4[3:0] | ||||||
2E | X | HPF_EN_ CH1 |
HPF_CORNER _CH1[3:0] | FILTER1_COEFF_SET[2:0] | FILTER1_RATE[2:0] | X | ODD_TAP1 | X | USE_ FILTER1 |
|||||||
30 | X | HPF_EN_ CH2 |
HPF_CORNER _CH2[3:0] | FILTER2_COEFF_SET[2:0] | FILTER2_RATE[2:0] | X | ODD_TAP2 | X | USE_ FILTER2 |
|||||||
33 | X | HPF_EN_ CH3 |
HPF_CORNER _CH3[3:0] | FILTER3_COEFF_SET[2:0] | FILTER3_RATE[2:0] | X | ODD_TAP3 | X | USE_ FILTER3 |
|||||||
35 | X | HPF_EN_ CH4 |
HPF_CORNER _CH4[3:0] | FILTER4_COEFF_SET[2:0] | FILTER4_RATE[2:0] | X | ODD_TAP4 | X | USE_ FILTER4 |
|||||||
38 | X | X | X | X | X | X | X | X | X | X | X | X | X | X | DATA_RATE[1:0] | |
42 | EN_REF_ VCM0 |
X | X | X | X | X | X | X | X | PHASE_DDR[1:0] | X | EN_REF_ VCM1 |
X | X | X | |
45 | X | X | X | X | X | X | X | X | X | X | X | X | X | X | PAT_SYNC | PAT_ DESKEW |
46 | ENABLE 46 | X | FALL_SDR | X | EN_16BIT | EN_14BIT | EN_12BIT | X | X | X | X | EN_SDR | MSB_ FIRST |
BTC_ MODE |
X | EN_2LANE |
50 | ENABLE 50 | X | X | X | X | X | X | X | MAP_CH12_TO_OUT1B[3:0] | MAP_CH12_TO_OUT1A[3:0] | ||||||
51 | ENABLE 51 | X | X | X | MAP_CH12_TO_OUT2B[3:0] | MAP_CH12_TO_OUT2A[3:0] | X | X | X | X | ||||||
53 | ENABLE 53 | X | X | X | MAP_CH34_TO_OUT3B[3:0] | X | X | X | X | X | X | X | X | |||
54 | ENABLE 54 | X | X | X | X | X | X | X | X | X | X | X | MAP_CH34_TO_OUT3A[3:0] | |||
55 | ENABLE 55 | X | X | X | X | X | X | X | MAP_CH34_TO_OUT4A[3:0] | MAP_CH34_TO_OUT4B[3:0] | ||||||
F0 | EN_EXT_ REF |
X | X | X | X | X | X | X | X | X | X | X | X | X | X | X |
This is a general register.
D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 |
X | |||||||
W-0 | |||||||
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
X | RST | ||||||
W-0 | W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
D15-D1 | X | W | 0 | Don't care bits |
D0 | RST | W | 0 |
Reset 0 = Normal operation (default) 1 = Self-clearing software reset (after reset, this bit is set to 0) |
This is a general register.
D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 |
X | |||||||
W-0 | |||||||
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
X | EN_HIGH_ADDRS | X | READOUT | ||||
W-0 | W-0 | W-0 | W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
D15-D5 | X | W | 0 | Don't care bits |
D4 | EN_HIGH_ADDRS | W | 0 |
Register F0h access 0 = Disables access to register F0h (default) 1 = Enables access to register F0h |
D3-D1 | X | W | 0 | Don't care bits |
D0 | READOUT | W | 0 |
Register mode readout 0 = Normal operation (default) 1 = Register mode readout |
This is a general register.
D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 |
X | EN_SYNC | X | |||||
R/W-0 | R/W-0 | R/W-0 | |||||
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
X | |||||||
R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
D15-D14 | X | R/W | 0 | Don't care bits |
D13 | EN_SYNC | R/W | 0 |
SYNC enable(1) 0 = Normal operation; SYNC feature disabled (default) 1 = SYNC feature enabled to synchronize test patterns |
D12-D0 | X | R/W | 0 | Don't care bits |
This is a general register.
D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 |
RAMP_PAT_RESET_VAL | |||||||
R/W-0 | |||||||
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
RAMP_PAT_RESET_VAL | |||||||
R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
D15-D0 | RAMP_PAT_RESET_VAL | R/W | 0 | These bits determine the initial value of the ramp pattern after reset. |
This is a power-down mode register. All bits default to 0 after reset.
D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 |
X | PDN_PIN_CFG | PDN_ COMPLETE | PDN_PARTIAL | ||||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | ||||
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
PDN_CH4 | X | PDN_CH3 | X | PDN_CH2 | X | PDN_CH1 | |
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
D15-D11 | X | R/W | 0 | Don't care bits |
D10 | PDN_PIN_CFG | R/W | 0 |
PD pin configuration 0 = PD pin configured for complete power-down mode 1 = PD pin configured for partial power-down mode |
D9 | PDN_ COMPLETE | R/W | 0 |
Complete power-down 0 = Normal operation 1 = Register mode for complete power-down (slower recovery) |
D8 | PDN_PARTIAL | R/W | 0 |
Partial power-down 0 = Normal operation 1 = Partial power-down mode (fast recovery from power-down) |
D7 | PDN_CH4 | R/W | 0 |
ADC power-down mode for channel 4 0 = Normal operation 1 = Partial power-down mode (fast recovery from power-down) |
D6 | X | R/W | 0 | Don't care bit |
D5 | PDN_CH3 | R/W | 0 |
ADC power-down mode for channel 3 0 = Normal operation 1 = ADC power-down mode for channel 3 |
D4-D3 | X | R/W | 0 | Don't care bits |
D2 | PDN_CH2 | R/W | 0 |
ADC power-down mode for channel 2 0 = Normal operation 1 = ADC power-down mode for channel 2 |
D1 | X | R/W | 0 | Don't care bit |
D0 | PDN_CH1 | R/W | 0 |
ADC power-down mode for channel 1 0 = Normal operation 1 = ADC power-down mode for channel 1 |
This is a general register.
D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 |
X | |||||||
R/W-0 | |||||||
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
LFNS_CH4 | X | LFNS_CH3 | X | LFNS_CH2 | X | LFNS_CH1 | |
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
D15-D8 | X | R/W | 0 | Don't care bits |
D7 | LFNS_CH4 | R/W | 0 |
Noise-suppression mode selection for channel 4 0 = LFNS disabled (default) 1 = Low-frequency noise-suppression mode enable for channel 4 |
D6 | X | R/W | 0 | Don't care bit |
D5 | LFNS_CH3 | R/W | 0 |
Noise-suppression mode selection for channel 3 0 = LFNS disabled (default) 1 = Low-frequency noise-suppression mode enable for channel 3 |
D4-D3 | X | R/W | 0 | Don't care bits |
D2 | LFNS_CH2 | R/W | 0 |
Noise-suppression mode selection for channel 2 0 = LFNS disabled (default) 1 = Low-frequency noise-suppression mode enable for channel 2 |
D1 | X | R/W | 0 | Don't care bit |
D0 | LFNS_CH1 | R/W | 0 |
Noise-suppression mode selection for channel 1 0 = LFNS disabled (default) 1 = Low-frequency noise-suppression mode enable for channel 1 |
This is a test pattern register. All bits default to 0 after reset.
D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 |
X | EN_FRAME_PAT | ADCLKOUT[11:0] | |||||
R/W-0 | R/W-0 | R/W-0 | |||||
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
ADCLKOUT[11:0] | X | ||||||
R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
D15 | X | R/W | 0 | Don't care bit |
D14 | EN_FRAME_PAT | R/W | 0 |
Frame pattern enable 0 = Normal frame clock operation 1 = Enables the output frame clock to be programmed through a pattern |
D13-D2 | ADCLKOUT[11:0] | R/W | 0 |
ADCLK pin frame clock pattern These bits determine the 12-bit pattern for the frame clock on the ADCLKP and ADCLKN pins. |
D1-D0 | X | R/W | 0 | Don't care bits |
This is a test pattern register.
D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 |
PRBS_SEED[15:0] | |||||||
R/W-0 | |||||||
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
PRBS_SEED[15:0] | |||||||
R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
D15-D0 | PRBS_SEED[15:0] | R/W | 0 |
PRBS pattern seed value, lower bits These bits determine the PRBS pattern starting seed value of the lower 16 bits. (Default = 0) |
This is a test pattern register. All bits default to 0 after reset.
D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 |
PRBS_SEED[22:16] | X | ||||||
R/W-0 | R/W-0 | ||||||
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
INVERT_CH4 | X | INVERT_CH3 | X | INVERT_CH2 | X | INVERT_CH1 | |
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
D15-D9 | PRBS_SEED[22:16] | R/W | 0 |
PRBS pattern seed value, upper bits These bits determine the PRBS pattern starting seed value of the upper seven bits. |
D8 | X | R/W | 0 | Don't care bit |
D7 | INVERT_CH4 | R/W | 0 |
Analog input pin polarity for channel 4 0 = Normal configuration (default) 1 = Electrically swaps the analog input pin polarity for channel 4 |
D6 | X | R/W | 0 | Don't care bit |
D5 | INVERT_CH3 | R/W | 0 |
Analog input pin polarity for channel 3 0 = Normal configuration (default) 1 = Electrically swaps the analog input pin polarity for channel 3 |
D4-D3 | X | R/W | 0 | Don't care bits |
D2 | INVERT_CH2 | R/W | 0 |
Analog input pin polarity for channel 2 0 = Normal configuration (default) 1 = Electrically swaps the analog input pin polarity for channel 2 |
D1 | X | R/W | 0 | Don't care bit |
D0 | INVERT_CH1 | R/W | 0 |
Analog input pin polarity for channel 1 0 = Normal configuration (default) 1 = Electrically swaps the analog input pin polarity for channel 1 |
This is a test pattern register. All bits default to 0 after reset.
D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 |
HARD_SYNC_TP | PRBS_SEED_FROM_REG | PRBS_MODE_2 | PRBS_TP_EN | X | TP_SOFT_SYNC | ||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | ||
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
X | EN_RAMP | DUAL_CUSTOM_PAT | SINGLE_CUSTOM_PAT | BITS_CUSTOM2[13:12] | BITS_CUSTOM1[13:12] | ||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
D15 | HARD_SYNC_TP | R/W | 0 |
Sync test pattern selection 0 = Inactive 1 = External SYNC feature enabled for syncing test patterns |
D14 | PRBS_SEED_FROM_REG | R/W | 0 |
PRBS seed selection 0 = Disabled 1 = Selection of PRBS seed from registers 23h and 24h enabled |
D13 | PRBS_MODE_2 | R/W | 0 |
PRBS mode selection This bit sets the PRBS mode of the 9-bit LFSR (the 23-bit LFSR is default). |
D12 | PRBS_TP_EN | R/W | 0 |
PRBS test pattern selection 0 = PRBS test pattern disabled 1 = PRBS test pattern enable bit |
D11-D9 | X | R/W | 0 | Don't care bits |
D8 | TP_SOFT_SYNC | R/W | 0 |
Test pattern software sync 0 = No sync 1 = Software sync bit for test patterns on all eight channels |
D7 | X | R/W | 0 | Don't care bit |
D6 | EN_RAMP | R/W | 0 |
Ramp pattern enable 0 = Normal operation 1 = Enables a repeating full-scale ramp pattern on the outputs. Ensure that bits D4 and D5 are 0. |
D5 | DUAL_CUSTOM_PAT | R/W | 0 |
Output toggles between two codes 0 = Normal operation 1 = Enables mode where the output toggles between two defined codes. Ensure that bits D4 and D6 are 0. |
D4 | SINGLE_CUSTOM_PAT | R/W | 0 |
Output is defined code 0 = Normal operation 1 = Enables mode where the output is a constant specified code. Ensure that bits D5 and D6 are 0. |
D3-D2 | BITS_CUSTOM2[13:12] | R/W | 0 |
MSB selection for dual patterns These bits determine two MSBs for the second code of the dual custom patterns. |
D1-D0 | BITS_CUSTOM1[13:12] | R/W | 0 |
MSB selection for single patterns These bits define two MSBs for the single custom pattern (and for the first code of the dual custom patterns). |
This is a test pattern register.
D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 |
BITS_CUSTOM1[9:0] | |||||||
R/W-0 | |||||||
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
BITS_CUSTOM1[9:0] | X | ||||||
R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
D15-D6 | BITS_CUSTOM1[9:0] | R/W | 0 |
Lower single custom pattern bits These bits determine the 10 lower bits for the single custom pattern (and the first code of the dual custom pattern). |
D5-D0 | X | R/W | 0 | Don't care bits |
This is a test pattern register.
D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 |
BITS_CUSTOM2[9:0] | |||||||
R/W-0 | |||||||
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
BITS_CUSTOM2[9:0] | X | ||||||
R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
D15-D6 | BITS_CUSTOM2[9:0] | R/W | 0 | Lower dual custom pattern bits These bits determine the 10 lower bits for the second code of the dual custom pattern. |
D5-D0 | X | R/W | 0 | Don't care bits |
This is an output interface mode register. All bits default to 0 after reset.
D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 |
EN_BITORDER | X | BIT_WISE | |||||
R/W-0 | R/W-0 | R/W-0 | |||||
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
EN_WORDWISE_BY_CH[7:0] | |||||||
R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
D15 | EN_BITORDER | R/W | 0 |
Bit order enable(1) This bit enables the bit order output in two-lane mode. 0 = Byte-wise 1 = Word-wise |
D14-D9 | X | R/W | 0 | Don't care bit |
D8 | BIT_WISE | R/W | 0 |
Bit- or byte-wise selection This bit selects between byte-wise and bit-wise format. 0 = Byte-wise, the upper bits come are on one lane and the lower bits are on other lane 1 = Bit-wise, the odd bits come out on one lane and the even bits come out on other lane |
D7-D0 | EN_WORDWISE_BY_CH[7:0] | R/W | 0 |
Word-wise enable with channels 7 to 0 0 = Data comes out in two-lane mode with the upper set of bits on one channel and the lower set of bits on the other channel 1 = Output format is one sample on one LVDS lane with the next sample on the other LVDS lane |
This is a digital filter mode register. All bits default to 0 after reset.
D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 |
X | |||||||
R/W-0 | |||||||
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
X | GLOBAL_EN_FILTER | X | |||||
R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
D15-D2 | X | R/W | 0 | Don't care bits |
D1 | GLOBAL_EN_FILTER | R/W | 0 |
Filter block enable 0 = Inactive 1 = Global control filter blocks enabled |
D0 | X | R/W | 0 | Don't care bit |
This is a digital gain mode register. All bits default to 0 after reset.
D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 |
X | GAIN_CH2[3:0] | ||||||
R/W-0 | R/W-0 | ||||||
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
X | GAIN_CH1[3:0] | ||||||
R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
D15-D12 | X | R/W | 0 | Don't care bits |
D11-D8 | GAIN_CH2[3:0] | R/W | 0 |
Channel 2 gain These bits set the programmable gain of channel 2 |
D7-D4 | X | R/W | 0 | Don't care bits |
D3-D0 | GAIN_CH3[3:0] | R/W | 0 |
Channel 1 gain These bits set the programmable gain of channel 1 |
This is a digital gain mode register. All bits default to 0 after reset.
D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 |
X | GAIN_CH3[3:0] | ||||||
R/W-0 | R/W-0 | ||||||
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
X | GAIN_CH4[3:0] | ||||||
R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
D15-D12 | X | R/W | 0 | Don't care bits |
D11-D8 | GAIN_CH3[3:0] | R/W | 0 |
Channel 3 gain These bits set the programmable gain of channel 3 |
D7-D4 | X | R/W | 0 | Don't care bits |
D3-D0 | GAIN_CH4[3:0] | R/W | 0 |
Channel 4 gain These bits set the programmable gain of channel 4 |
This is a digital filter mode register. All bits default to 0 after reset.
D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 |
X | HPF_EN_CH1 | HPF_CORNER _CH1[3:0] | FILTER1_COEFF_SET[2:0] | ||||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | ||||
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
FILTER1_COEFF_SET[2:0] | FILTER1_RATE[2:0] | X | ODD_TAP1 | X | USE_FILTER1 | ||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
D15 | X | R/W | 0 | Don't care bit |
D14 | HPF_EN_CH1 | R/W | 0 |
Channel 1 HPF filter enable 0 = Disabled 1 = HPF filter enable for channel 1 |
D13-D10 | HPF_CORNER _CH1[3:0] | R/W | 0 |
HPF corner for channel 1 These bits set the HPF corner in values from 2k to 10k. |
D9-D7 | FILTER1_COEFF_SET[2:0] | R/W | 0 |
Filter 1 coefficient set These bits select the stored coefficient set for filter 1. |
D6-D4 | FILTER1_RATE[2:0] | R/W | 0 |
Filter 1 decimation factor These bits set the decimation factor for filter 2. |
D3 | X | R/W | 0 | Don't care bit |
D2 | ODD_TAP1 | R/W | 0 |
Filter 1 odd tap This bit uses odd tap filter 1. |
D1 | X | R/W | 0 | Don't care bit |
D0 | USE_FILTER1 | R/W | 0 |
Channel 1 filter 0 = Disabled 1 = Enables filter for channel 1 |
This is a digital filter mode register. All bits default to 0 after reset.
D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 |
X | HPF_EN_CH2 | HPF_CORNER _CH2[3:0] | FILTER2_COEFF_SET[2:0] | ||||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | ||||
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
FILTER2_COEFF_SET[2:0] | FILTER2_RATE[2:0] | X | ODD_TAP2 | X | USE_FILTER2 | ||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
D15 | X | R/W | 0 | Don't care bit |
D14 | HPF_EN_CH2 | R/W | 0 |
Channel 2 HPF filter enable 0 = Disabled 1 = HPF filter enable for channel 2 |
D13-D10 | HPF_CORNER _CH2[3:0] | R/W | 0 |
HPF corner for channel 2 These bits set the HPF corner in values from 2k to 10k. |
D9-D7 | FILTER2_COEFF_SET[2:0] | R/W | 0 |
Filter 2 coefficient set These bits select the stored coefficient set for filter 2. |
D6-D4 | FILTER2_RATE[2:0] | R/W | 0 |
Filter 2 decimation factor These bits set the decimation factor for filter 2. |
D3 | X | R/W | 0 | Don't care bit |
D2 | ODD_TAP2 | R/W | 0 |
Filter 2 odd tap This bit uses odd tap filter 2. |
D1 | X | R/W | 0 | Don't care bit |
D0 | USE_FILTER2 | R/W | 0 |
Channel 2 filter 0 = Disabled 1 = Enables filter for channel 2 |
This is a digital filter mode register. All bits default to 0 after reset.
D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 |
X | HPF_EN_CH3 | HPF_CORNER _CH3[3:0] | FILTER3_COEFF_SET[2:0] | ||||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | ||||
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
FILTER3_COEFF_SET[2:0] | FILTER3_RATE[2:0] | X | ODD_TAP3 | USE_FILTER3 | |||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
D15 | X | R/W | 0 | Don't care bit |
D14 | HPF_EN_CH3 | R/W | 0 |
Channel 3 HPF filter enable 0 = Disabled 1 = HPF filter enable for channel 3 |
D13-D10 | HPF_CORNER _CH3[3:0] | R/W | 0 |
HPF corner for channel 3 These bits set the HPF corner in values from 2k to 10k. |
D9-D7 | FILTER3_COEFF_SET[2:0] | R/W | 0 |
Filter 3 coefficient set These bits select the stored coefficient set for filter 3. |
D6-D4 | FILTER3_RATE[2:0] | R/W | 0 |
Filter 3 decimation factor These bits set the decimation factor for filter 3. |
D3 | X | R/W | 0 | Don't care bit |
D2 | ODD_TAP3 | R/W | 0 |
Filter 3 odd tap This bit uses odd tap filter 3. |
D1 | X | R/W | 0 | Don't care bit |
D0 | USE_FILTER3 | R/W | 0 |
Channel 3 filter 0 = Disabled 1 = Enables filter for channel 3 |
This is a digital filter mode register. All bits default to 0 after reset.
D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 |
X | HPF_EN_CH4 | HPF_CORNER _CH4[3:0] | FILTER4_COEFF_SET[2:0] | ||||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | ||||
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
FILTER4_COEFF_SET[2:0] | FILTER4_RATE[2:0] | X | ODD_TAP4 | X | USE_FILTER4 | ||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
D15 | X | R/W | 0 | Don't care bit |
D14 | HPF_EN_CH4 | R/W | 0 |
Channel 4 HPF filter enable 0 = Disabled 1 = HPF filter enable for channel 4 |
D13-D10 | HPF_CORNER _CH4[3:0] | R/W | 0 |
HPF corner for channel 4 These bits set the HPF corner in values from 2k to 10k. |
D9-D7 | FILTER4_COEFF_SET[2:0] | R/W | 0 |
Filter 4 coefficient set These bits select the stored coefficient set for filter 4. |
D6-D4 | FILTER4_RATE[2:0] | R/W | 0 |
Filter 4 decimation factor These bits set the decimation factor for filter 4. |
D3 | X | R/W | 0 | Don't care bit |
D2 | ODD_TAP4 | R/W | 0 |
Filter 4 odd tap This bit uses odd tap filter 4. |
D1 | X | R/W | 0 | Don't care bit |
D0 | USE_FILTER4 | R/W | 0 |
Channel 4 filter 0 = Disabled 1 = Enables filter for channel 4 |
This is an output interface mode register.
D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 |
X | |||||||
R/W- | |||||||
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
X | DATA_RATE[1:0] | ||||||
R/W- | R/W- |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
D15-D2 | X | R/W | 0 | Don't care bits |
D1-D0 | DATA_RATE[1:0] | R/W | 0 |
Clock rate selection These bits select the output frame clock rate. (Default = 0) |
This is an output interface mode register.
D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 |
EN_REF_VCM0 | X | ||||||
R/W-0 | R/W-0 | ||||||
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
X | PHASE_DDR[1:0] | X | EN_REF_VCM1 | X | |||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
D15 | EN_REF_VCM0 | R/W | 0 |
To enable the external reference mode, the EN_EXT_REF register bit (register F0h) must be set to 1. 00 = In external reference mode, apply the reference on the REFT, REFB pins 01, 10 = Don't use 11 = In external reference mode, apply the reference on the VCM pin |
D14-D7 | X | R/W | 0 | Don't care bits |
D6-D5 | PHASE_DDR[1:0] | R/W | 0 | These bits control the LCLK output phase relative to data. (Default = 10) |
D4 | X | R/W | 0 | Don't care bit |
D3 | EN_REF_VCM1 | R/W | 0 |
To enable the external reference mode, the EN_EXT_REF register bit (register F0h) must be set to 1. 00 = In external reference mode, apply the reference on the REFT, REFB pins 01, 10 = Don't use 11 = In external reference mode, apply the reference on the VCM pin |
D2-D0 | X | R/W | 0 | Don't care bits |
This is a test pattern register. All bits default to 0 after reset.
D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 |
X | |||||||
R/W-0 | |||||||
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
X | PAT_SYNC | PAT_DESKEW | |||||
R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
D15-D2 | X | R/W | 0 | Don't care bits |
D1 | PAT_SYNC | R/W | 0 |
Sync pattern enable 0 = Inactive 1 = Sync pattern mode enabled; ensure that D0 is 0 |
D0 | PAT_DESKEW | R/W | 0 |
Deskew pattern enable 0 = Inactive 1 = Deskew pattern mode enabled; ensure that D1 is 0 |
This is an output interface mode register. All bits default to 0 after reset.
D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 |
ENABLE 46 | X | FALL_SDR | X | EN_16BIT | EN_14BIT | EN_12BIT | X |
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
X | EN_SDR | MSB_FIRST | BTC_MODE | X | EN_2LANE | ||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
D15 | ENABLE 46 | R/W | 0 |
Enable register 46(1) This bit enables register 46. |
D14 | X | R/W | 0 | Don't care bit |
D13 | FALL_SDR | R/W | 0 |
SDR output mode 0 = At data window edge 1 = The LCLK rising or falling edge control comes in the middle of the data window when operating in SDR output mode |
D12 | X | R/W | 0 | Don't care bit |
D11 | EN_16BIT | R/W | 0 |
16-bit mode enable 0 = Inactive 1 = 16-bit serialization mode enabled; ensure bits D[10:9] are 0 |
D10 | EN_14BIT | R/W | 0 |
14-bit mode enable 0 = Inactive 1 = 14-bit serialization mode enabled; ensure bits D11 and D9 are 0 |
D9 | EN_12BIT | R/W | 0 |
12-bit mode enable 0 = Inactive 1 = 12-bit serialization mode enabled; ensure bits D[11:10] are 0 |
D8-D5 | X | R/W | 0 | Don't care bits |
D4 | EN_SDR | R/W | 0 |
Bit clock selection 0 = DDR bit clock 1 = SDR bit clock |
D3 | MSB_FIRST | R/W | 0 |
MSB first selection 0 = LSB first 1 = MSB first |
D2 | BTC_MODE | R/W | 0 |
Binary mode selection 0 = Binary offset (ADC data output format) 1 = Binary twos complement (ADC data output format) |
D1 | X | R/W | 0 | Don't care bit |
D0 | EN_2LANE | R/W | 0 |
LVDS output lane selection 0 = One-lane LVDS output 1 = Two-lane LVDS output |
This is a programmable LVDS mapping mode register. All bits default to 0 after reset.
D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 |
ENABLE 50 | X | ||||||
R/W-0 | R/W-0 | ||||||
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
MAP_CH12_TO_OUT1B[3:0] | MAP_CH12_TO_OUT1A[3:0] | ||||||
R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
D15 | ENABLE 50 | R/W | 0 |
Enable for register 50h(1) This bit enables register 50h. |
D14-D8 | X | R/W | 0 | Don't care bits |
D7-D4 | MAP_CH12_TO_OUT1B[3:0] | R/W | 0 |
OUT1B pin to channel mapping These bits select the OUT1B pin pair to channel data mapping. |
D3-D0 | MAP_CH12_TO_OUT1A[3:0] | R/W | 0 |
OUT1A pin to channel mapping These bits select the OUT1A pin pair to channel data mapping. |
This is a programmable LVDS mapping mode register. All bits default to 0 after reset.
D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 |
ENABLE 51 | X | MAP_CH12_TO_OUT2B[3:0] | |||||
R/W-0 | R/W-0 | R/W-0 | |||||
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
MAP_CH12_TO_OUT2A[3:0] | X | ||||||
R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
D15 | ENABLE 51 | R/W | 0 |
Enable for register 51h(1) This bit enables register 51h. |
D14-D12 | X | R/W | 0 | Don't care bits |
D11-D8 | MAP_CH12_TO_OUT2B[3:0] | R/W | 0 |
OUT2B pin to channel mapping These bits select the OUT2B pin pair to channel data mapping. |
D7-D4 | MAP_CH12_TO_OUT2A[3:0] | R/W | 0 |
OUT2A pin to channel mapping These bits select the OUT2A pin pair to channel data mapping. |
D3-D0 | X | R/W | 0 | Don't care bits |
This is a programmable LVDS mapping mode register. All bits default to 0 after reset.
D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 |
ENABLE 53 | X | MAP_CH34_TO_OUT3B[3:0] | |||||
R/W-0 | R/W-0 | R/W-0 | |||||
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
X | |||||||
R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
D15 | ENABLE 53 | R/W | 0 |
Enable register 53h(1) This bit enables register 53h. |
D14-D12 | X | R/W | 0 | Don't care bits |
D11-D8 | MAP_CH34_TO_OUT3B[3:0] | R/W | 0 |
OUT3B pin to channel mapping These bits select the OUT3B pin pair to channel data mapping. |
D7-D0 | X | R/W | 0 | Don't care bits |
This is a programmable LVDS mapping mode register. All bits default to 0 after reset.
D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 |
ENABLE 54 | X | ||||||
R/W-0 | R/W-0 | ||||||
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
X | MAP_Ch34_to_OUT3A[3:0] | ||||||
R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
D15 | ENABLE 54 | R/W | 0 |
Enable register 54h(1) This bit enables register 54h. |
D14-D4 | X | R/W | 0 | Don't care bits |
D3-D0 | MAP_Ch34_to_OUT3A[3:0] | R/W | 0 |
OUT3A pin to channel mapping These bits select the OUT3A pin pair to channel data mapping. |
This is a programmable LVDS mapping mode register. All bits default to 0 after reset.
D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 |
ENABLE 55 | X | ||||||
R/W-0 | R/W-0 | ||||||
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
MAP_CH34_TO_OUT4A[3:0] | MAP_CH34_TO_OUT4B[3:0] | ||||||
R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
D15 | ENABLE 55 | R/W | 0 |
Enable register 55h(1) This bit enables register 55h. |
D14-D8 | X | R/W | 0 | Don't care bits |
D7-D4 | MAP_CH34_TO_OUT4A[3:0] | R/W | 0 |
OUT4A pin to channel mapping These bits select the OUT4A pin pair to channel data mapping. |
D3-D0 | MAP_CH34_TO_OUT4B[3:0] | R/W | 0 |
OUT4B pin to channel mapping These bits select the OUT4B pin pair to channel data mapping. |
This is a general register.
NOTE
The EN_HIGH_ADDRS bit (register 01h, bit D4) must be set to 1 in order to access this register.
D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 |
EN_EXT_REF | X | ||||||
R/W-0 | R/W-0 | ||||||
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
X | |||||||
R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
D15 | EN_EXT_REF | R/W | 0 |
Reference mode selection 0 = Internal reference mode enabled (default) 1 = External reference mode enabled. The voltage reference can be applied on either the REFP and REFB pins or the VCM pin. |
D7-D0 | X | R/W | 0 | Don't care bits |