SLES275A January   2015  – December 2017 VSP5324-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Dynamic Performance
    6. 6.6  Electrical Characteristics: General
    7. 6.7  Electrical Characteristics: Digital
    8. 6.8  Timing Requirements
    9. 6.9  LVDS Timing at Different Sampling Frequencies (One-Lane Interface, 12x Serialization)
    10. 6.10 LVDS Timing at Different Sampling Frequencies (Two-Lane Interface, 6x Serialization)
    11. 6.11 Serial Interface Timing Requirements
    12. 6.12 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
        1. 7.3.1.1 Large- and Small-Signal Input Bandwidth
      2. 7.3.2 Digital Processing Block
        1. 7.3.2.1 Digital Gain
        2. 7.3.2.2 ADC Input Polarity Inversion
        3. 7.3.2.3 SYNC Function
        4. 7.3.2.4 Output Data Format
      3. 7.3.3 Serial LVDS Interface
        1. 7.3.3.1 One-Lane, 12x Serialization with DDR Bit Clock and 1x Frame Clock
        2. 7.3.3.2 Two-Lane, 6x Serialization with DDR Bit Clock and 0.5x Frame Clock
      4. 7.3.4 Bit Clock Programmability
      5. 7.3.5 LVDS Output Data and Clock Buffers
    4. 7.4 Device Functional Modes
      1. 7.4.1 External Reference Mode Of Operation
        1. 7.4.1.1 Using the REF Pins
        2. 7.4.1.2 Using the VCM Pin
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
      2. 7.5.2 Register Initialization
      3. 7.5.3 Serial Register Readout
    6. 7.6 Register Maps
      1. 7.6.1 Serial Registers
        1. 7.6.1.1  Register 00h (offset = 00h) [reset = 0]
        2. 7.6.1.2  Register 01h (offset = 01h) [reset = 0]
        3. 7.6.1.3  Register 02h (offset = 02h) [reset = 0]
        4. 7.6.1.4  Register 0Ah (offset = 0Ah) [reset = 0]
        5. 7.6.1.5  Register 0Fh (offset = 0Fh) [reset = 0]
        6. 7.6.1.6  Register 14h (offset = 14h) [reset = 0]
        7. 7.6.1.7  Register 1Ch (offset = 1Ch) [reset = 0]
        8. 7.6.1.8  Register 23h (offset = 23h) [reset = 0]
        9. 7.6.1.9  Register 24h (offset = 24h) [reset = 0]
        10. 7.6.1.10 Register 25h (offset = 25h) [reset = 0]
        11. 7.6.1.11 Register 26h (offset = 26h) [reset = 0]
        12. 7.6.1.12 Register 27h (offset = 27h) [reset = 0]
        13. 7.6.1.13 Register 28h (offset = 28h) [reset = 0]
        14. 7.6.1.14 Register 29h (offset = 29h) [reset = 0]
        15. 7.6.1.15 Register 2Ah (offset = 2Ah) [reset = 0]
        16. 7.6.1.16 Register 2Bh (offset = 2Bh) [reset = 0]
        17. 7.6.1.17 Register 2Eh (offset = 2Eh) [reset = 0]
        18. 7.6.1.18 Register 30h (offset = 30h) [reset = 0]
        19. 7.6.1.19 Register 33h (offset = 33h) [reset = 0]
        20. 7.6.1.20 Register 35h (offset = 35h) [reset = 0]
        21. 7.6.1.21 Register 38h (offset = 38h) [reset = 0x0000]
        22. 7.6.1.22 Register 42h (offset = 42h) [reset = 0]
        23. 7.6.1.23 Register 45h (offset = 45h) [reset = 0]
        24. 7.6.1.24 Register 46h (offset = 46h) [reset = 0]
        25. 7.6.1.25 Register 50h (offset = 50h) [reset = 0]
        26. 7.6.1.26 Register 51h (offset = 51h) [reset = 0]
        27. 7.6.1.27 Register 53h (offset = 53h) [reset = 0]
        28. 7.6.1.28 Register 54h (offset = ) [reset = 0]
        29. 7.6.1.29 Register 55h (offset = 55h) [reset = 0]
        30. 7.6.1.30 Register F0h (offset = F0h) [reset = 0]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Drive Circuit Requirements
        2. 8.2.2.2 Clock Input
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 General Guidelines
      2. 10.1.2 Grounding
      3. 10.1.3 Supply Decoupling
      4. 10.1.4 Exposed Pad
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

11 Device and Documentation Support

11.1 Device Support

11.1.1 Device Nomenclature

    Analog bandwidth The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the low-frequency value.
    Aperture delay The delay in time between the input sampling clock rising edge and the actual time at which the sampling occurs. This delay is different across channels. The maximum variation is specified as aperture delay variation (channel-to-channel).
    Aperture uncertainty (jitter) The sample-to-sample variation in aperture delay.
    Clock pulse width and duty cycle The clock signal duty cycle is the ratio of the time the clock signal remains at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a percentage. A perfect differential sine-wave clock results in a 50% duty cycle.
    Maximum conversion rate The maximum sampling rate at which the specified operation is given. All parametric testing is performed at this sampling rate unless otherwise noted.
    Minimum conversion rate The minimum sampling rate at which the ADC functions.
    Differential nonlinearity (DNL) An ideal ADC exhibits code transitions at analog input values spaced exactly 1 LSB apart. DNL is the deviation of any single step from this ideal value, measured in units of LSBs.
    Integral nonlinearity (INL) INL is the deviation of the ADC transfer function from a best-fit line determined by a least-squares curve fit of that transfer function, measured in units of LSBs.
    Gain error Gain error is the deviation of the ADC actual input full-scale range from its ideal value. Gain error is given as a percentage of the ideal input full-scale range and has two components: error as a result of reference inaccuracy and error as a result of the channel. Both errors are specified independently as EG(REF) and EG(CHAN). To a first-order approximation, the total gain error is (Etot ~ EG(REF) + EG(CHAN)). For example, if Etot = ±0.5%, the full-scale input varies from [(1 – 0.5 / 100) × ƒS(ideal)] to [(1 + 0.5 / 100) × ƒS(ideal)].
    Offset error Offset error is the difference, given in number of LSBs, between the ADC actual average idle channel output code and the ideal average idle channel output code. This quantity is often mapped into millivolts.
    Temperature drift The temperature drift coefficient (with respect to gain error and offset error) specifies the change per degree Celsius of the parameter from TMIN to TMAX. It is calculated by dividing the maximum parameter deviation across the TMIN to TMAX range by the difference of TMAX – TMIN.
    Signal-to-noise ratio (SNR) SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN), excluding the power at DC and the first nine harmonics. SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-scale range.
    Equation 3. VSP5324-Q1 q_snr_sles275.gif
    Signal-to-noise and distortion (SINAD) SINAD is the ratio of the power of the fundamental (PS) to the power of all other spectral components including noise (PN) and distortion (P(HD)), but excluding dc. SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-scale range.
    Equation 4. VSP5324-Q1 q_sinad_sles275.gif
    Effective number of bits (ENOB) ENOB is a measure of the converter performance as compared to the theoretical limit based on quantization noise.
    Equation 5. VSP5324-Q1 q_enob_sles275.gif
    Total harmonic distortion (THD) THD is the ratio of the power of the fundamental (PS) to the power of the first nine harmonics (P(HD)). THD is typically given in units of dBc (dB to carrier).
    Equation 6. VSP5324-Q1 q_thd_sles275.gif
    Spurious-free dynamic range (SFDR) The ratio of the power of the fundamental to the highest other spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier).
    Two-tone intermodulation distortion (IMD3) IMD3 is the ratio of the power of the fundamental (at frequencies ƒ1 and ƒ2) to the power of the worst spectral component at either frequency (2 ƒ1 – ƒ2 or 2 ƒ2 – ƒ1). IMD3 is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-scale range.
    DC power-supply rejection ratio (DC PSRR) DC PSSR is the ratio of the change in offset error to a change in analog supply voltage. The dc PSRR is typically given in units of mV/V.
    AC power-supply rejection ratio (ac PSRR) AC PSRR is the measure of rejection of variations in the supply voltage by the ADC. If ΔV(AVDD) is the change in supply voltage and ΔVO is the resultant change of the ADC output code (referred to input), then:
    Equation 7. VSP5324-Q1 q_psrr_sles275.gif
    Voltage overload recovery The number of clock cycles taken to recover to less than 1% error after an overload on the analog inputs. This recovery is tested by separately applying a sine-wave signal with a 6-dB positive and negative overload. The deviation of the first few samples after the overload (from the expected values) is noted.
    Common-mode rejection ratio (CMRR) CMRR is the measure of rejection of variation in the analog input common-mode by the ADC. If ΔVIC is the change in the common-mode voltage of the input pins and ΔVO is the resulting change of the ADC output code (referred to input), then:
    Equation 8. VSP5324-Q1 q_cmrr_sles275.gif
    Crosstalk (only for multichannel ADCs) Crosstalk is a measure of the internal coupling of a signal from an adjacent channel into the channel of interest. It is specified separately for coupling from the immediate neighboring channel (near-channel) and for coupling from channel across the package (far-channel). It is usually measured by applying a full-scale signal in the adjacent channel. Crosstalk is the ratio of the power of the coupling signal (as measured at the output of the channel of interest) to the power of the signal applied at the adjacent channel input. It is typically expressed in dBc.

11.2 Documentation Support

11.2.1 Related Documentation

For related documentation see the following:

11.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

11.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

    TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.
    Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

11.5 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.6 Electrostatic Discharge Caution

esds-image

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

11.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.