SLES275A January 2015 – December 2017 VSP5324-Q1
PRODUCTION DATA.
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
ADCLKM | 24 | Digital output | Negative LVDS differential frame clock output pin |
ADCLKP | 23 | Digital output | Positive LVDS differential frame clock output pin |
AGND | 3 | Ground | Analog ground pin |
6 | |||
9 | |||
37 | |||
40 | |||
43 | |||
46 | |||
AVDD | 50 | Supply | Analog supply pin, 1.8 V |
57 | |||
60 | |||
CLKM | 59 | Analog input | Negative clock input Differential clock input: apply differential clocks (sine wave, LVPECL, and LVDS) to CLKP and CLKM. Single-ended clock input: apply a CMOS clock to CLKP and tie CLKM to ground. |
CLKP | 58 | Analog input | Positive clock input Differential clock input: apply differential clocks (sine wave, LVPECL, and LVDS) to CLKP and CLKM. Single-ended clock input: apply a CMOS clock to CLKP and tie CLKM to ground. |
CS | 61 | Digital input | Serial interface enable pin |
IN1_M | 2 | Analog input | Channel 1 negative differential analog input |
IN1_P | 1 | Analog input | Channel 1 positive differential analog input |
IN2_M | 8 | Analog input | Channel 2 negative differential analog input |
IN2_P | 7 | Analog input | Channel 2 positive differential analog input |
IN3_M | 42 | Analog input | Channel 3 negative differential analog input |
IN3_P | 41 | Analog input | Channel 3 positive differential analog input |
IN4_M | 48 | Analog input | Channel 4 negative differential analog input |
IN4_P | 47 | Analog input | Channel 4 positive differential analog input |
INT/EXT | 56 | Digital input | Internal and external reference control input pin Logic high: device uses internal reference Logic low: device uses external reference |
LCLKM | 26 | Digital output | Negative LVDS differential bit clock output pin |
LCLKP | 25 | Digital output | Positive LVDS differential bit clock output pin |
LGND | 12 | Ground | Digital ground pin |
14 | |||
36 | |||
LVDD | 35 | Supply | Digital and LVDS supply pin, 1.8 V |
NC | 4 | — | Unused; do not connect |
5 | |||
10 | |||
11 | |||
38 | |||
39 | |||
44 | |||
45 | |||
51 | |||
OUT1A_M | 16 | Interface | Channel 1A negative LVDS differential output pin. This pin can be used with either one- or two-lane interface. |
OUT1A_P | 15 | Interface | Channel 1A positive LVDS differential output pin. This pin can be used with either one- or two-lane interface. |
OUT1B_M | 18 | Interface | Channel 1B negative LVDS differential output pin. This pin is used with two-lane interface. In one-lane interface, this pin is unused and must be floated without a 100-Ω termination. |
OUT1B_P | 17 | Interface | Channel 1B positive LVDS differential output pin. This pin is used with two-lane interface. In one-lane interface, this pin is unused and must be floated without a 100-Ω termination. |
OUT2A_M | 20 | Interface | Channel 2A negative LVDS differential output pin. This pin can be used with either one- or two-lane interface. |
OUT2A_P | 19 | Interface | Channel 2A positive LVDS differential output pin. This pin can be used with either one- or two-lane interface. |
OUT2B_M | 22 | Interface | Channel 2B negative LVDS differential output pin. This pin is used with two-lane interface. In one-lane interface, this pin is unused and must be floated without a 100-Ω termination. |
OUT2B_P | 21 | Interface | Channel 2B positive LVDS differential output pin. This pin is used with two-lane interface. In one-lane interface, this pin is unused and must be floated without a 100-Ω termination. |
OUT3A_M | 30 | Interface | Channel 3A negative LVDS differential output pin. This pin can be used with either one- or two-lane interface. |
OUT3A_P | 29 | Interface | Channel 3A positive LVDS differential output pin. This pin can be used with either one- or two-lane interface. |
OUT3B_M | 28 | Interface | Channel 3B negative LVDS differential output pin. This pin is used with two-lane interface. In one-lane interface, this pin is unused and must be floated without a 100-Ω termination. |
OUT3B_P | 27 | Interface | Channel 3B positive LVDS differential output pin. This pin is used with two-lane interface. In one-lane interface, this pin is unused and must be floated without a 100-Ω termination. |
OUT4A_M | 34 | Interface | Channel 4A negative LVDS differential output pin. This pin can be used with either one- or two-lane interface. |
OUT4A_P | 33 | Interface | Channel 4A positive LVDS differential output pin. This pin can be used with either one- or two-lane interface. |
OUT4B_M | 32 | Interface | Channel 4B negative LVDS differential output pin. This pin is used with two-lane interface. In one-lane interface, this pin is unused and must be floated without a 100-Ω termination. |
OUT4B_P | 31 | Interface | Channel 4B positive LVDS differential output pin. This pin is used with two-lane interface. In one-lane interface, this pin is unused and must be floated without a 100-Ω termination. |
PD | 13 | Digital input | Power-down control input pin Logic high: device is in power-down state; logic low: normal operation |
REFB | 54 | Analog input | Reference bottom voltage pin Internal reference mode: the reference bottom voltage (0.45 V) is output on this pin. External reference mode: the reference bottom voltage (0.45 V) must be externally applied to this pin. There are no required decoupling capacitors on this pin. |
REFT | 55 | Analog input | Reference top voltage pin Internal reference mode: the reference top voltage (1.45 V) is output on this pin. External reference mode: reference top voltage (1.45 V) must be externally applied to this pin. There are no required decoupling capacitors on this pin. |
RESET | 64 | Digital input | Serial interface reset pin; active low |
SCLK | 63 | Digital input | Serial interface clock pin |
SDATA | 62 | Digital input | Serial interface data pin |
SDOUT | 52 | Digital output | Serial interface readout pin |
SYNC | 49 | Digital input | Control input pin synchronizes test patterns across channels. When unused, this pin should be tied to ground. |
VCM | 53 | Analog output | Common-mode voltage pin Internal reference mode: common-mode voltage output pin, 0.95 V. External reference mode: reference voltage must be externally applied to this pin. |