JAJSTL8C February   1997  – October 2024 XTR105

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings #GUID-80F0CD5F-C345-42B2-B6A9-580512790460/R_DESCRIPTION_LI1
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Linearization
        1. 6.3.1.1 High-Resistance RTDs
      2. 6.3.2 Voltage Regulator
      3. 6.3.3 Open-Circuit Protection
      4. 6.3.4 Reverse-Voltage Protection
      5. 6.3.5 Surge Protection
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 External Transistor
      2. 7.1.2 Loop Power Supply
      3. 7.1.3 2-Wire and 3-Wire RTD Connections
      4. 7.1.4 Radio Frequency Interference
      5. 7.1.5 Error Analysis
    2. 7.2 Typical Applications
    3. 7.3 Layout
      1. 7.3.1 Layout Guidelines
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 Pin Configuration and Functions

Figure 4-1 D Package, 14-Pin SOIC, and N Package, 14-Pin PDIP (Top View)
Table 4-1 Pin Functions
PIN TYPE DESCRIPTION
NAME NO.
B (Base) 9 Output Base connection for external transistor
E (Emitter) 8 Input Emitter connection for external transistor
IO 7 Output Regulated 4mA to 20mA current loop output
IR1 1 Output 800µA reference current output, channel 1
IR2 14 Output 800µA reference current output, channel 2
IRET 6 Input Local ground return pin for VREG, VLIN, IR1, and IR2
NC 5 — Not internally connected
RG 3, 4 — Input stage gain setting pins. The resistance RG between pins 3 and 4 sets the gain of the voltage-to-current transfer function
V+ 10 Power Loop power supply
VIN– 2 Input Negative (inverting) differential voltage input
VIN+ 13 Input Positive (noninverting) differential voltage input
VLIN 12 Output Linearity correction voltage output
VREG 11 Output 5.1V regulator voltage output