SNAS333E August 2005 – December 2015 ADC128S052 , ADC128S052-Q1
PRODUCTION DATA.
The ADC128S052x device is a low-power, eight-channel CMOS 12-bit analog-to-digital converter specified for conversion throughput rates of
200 kSPS to 500 kSPS. The converter is based on a successive-approximation register architecture with an internal track-and-hold circuit. It can be configured to accept up to eight input signals at inputs IN0 through IN7.
The output serial data is straight binary and is compatible with several standards, such as SPI, QSPI, MICROWIRE, and many common DSP serial interfaces.
The ADC128S052x may be operated with independent analog and digital supplies. The analog supply (VA) can range from 2.7 V to 5.25 V, and the digital supply (VD) can range from 2.7 V to VA. Normal power consumption using a 3-V or
5-V supply is 1.6 mW and 8.7 mW, respectively. The power-down feature reduces the power consumption to 0.06 µW using a 3-V supply and 0.25 µW using a 5-V supply.
The ADC128S052x is packaged in a 16-pin TSSOP package. The ADC128S052 is ensured over the extended industrial temperature range of −40°C to +105°C while the ADC128S052-Q1 is ensured to an AECQ100 Grade-1 automotive temperature range of −40°C to +125°C.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
ADC128S052, ADC128S052-Q1 |
TSSOP (16) | 4.40 mm × 5.00 mm |
Changes from D Revision (March 2013) to E Revision
Changes from C Revision (March 2013) to D Revision
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | CS | Digital I/O | Chip select. On the falling edge of CS, a conversion process begins. Conversions continue as long as CS is held low. |
2 | VA | Power Supply | Positive analog supply pin. This voltage is also used as the reference voltage. This pin must be connected to a quiet 2.7-V to 5.25-V source and bypassed to GND with 1-µF and 0.1-µF monolithic ceramic capacitors located within 1 cm of the power pin. |
3 | AGND | Power Supply | The ground return for the analog supply and signals. |
4 | IN0 to IN7 | Analog I/O | Analog inputs. These signals can range from 0 V to VREF. |
5 | |||
6 | |||
7 | |||
8 | |||
9 | |||
10 | |||
11 | |||
12 | DGND | Power Supply | The ground return for the digital supply and signals. |
13 | VD | Power Supply | Positive digital supply pin. This pin must be connected to a 2.7-V to VA supply, and bypassed to GND with a 0.1-µF monolithic ceramic capacitor located within 1 cm of the power pin. |
14 | DIN | Digital I/O | Digital data input. The control register of the ADC128S052 is loaded through this pin on rising edges of the SCLK pin. |
15 | DOUT | Digital I/O | Digital data output. The output samples are clocked out of this pin on the falling edges of the SCLK pin. |
16 | SCLK | Digital I/O | Digital clock input. The ensured performance range of frequencies for this input is 3.2 MHz to 8 MHz. This clock directly controls the conversion and readout processes. |