ADC34J2x Quad-Channel, 12-Bit, 50-MSPS to 160-MSPS, Analog-to-Digital Converter with JESD204B Interface
- SBAS669A May 2014 – January 2015 ADC34J22 , ADC34J23 , ADC34J24 , ADC34J25
  
  PRODUCTION DATA.

Full reading width

DATA SHEET

ADC34J2x Quad-Channel, 12-Bit, 50-MSPS to 160-MSPS, Analog-to-Digital Converter with JESD204B Interface

1 Features

Quad Channel
12-Bit Resolution
Single 1.8-V Supply
Flexible Input Clock Buffer with Divide-by-1, -2, -4
SNR = 69.6 dBFS, SFDR = 86 dBc at
f_IN = 70 MHz
Ultra-Low Power Consumption:
- 203 mW/Ch at 160 MSPS
Channel Isolation: 105 dB
Internal Dither
JESD204B Serial Interface:
- Subclass 0, 1, 2 Compliant up to 3.2 Gbps
- Supports One Lane per ADC up to 160 MSPS
Support for Multi-Chip Synchronization
Pin-to-Pin Compatible with 14-Bit Version
Package: VQFN-48 (7 mm × 7 mm)

2 Applications

Multi-Carrier, Multi-Mode Cellular Base Stations
Radar and Smart Antenna Arrays
Munitions Guidance
Motor Control Feedback
Network and Vector Analyzers
Communications Test Equipment
Nondestructive Testing
Microwave Receivers
Software Defined Radios (SDRs)
Quadrature and Diversity Radio Receivers

3 Description

The ADC34J2x are a high-linearity, ultra-low power, dual-channel, 12-bit, 50-MSPS to 160-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. A clock input divider allows more flexibility for system clock architecture design while the SYSREF input enables complete system synchronization. The devices support JESD204B interfaces in order to reduce the number of interface lines, thus allowing for high system integration density. The JESD204B interface is a serial interface, where the data of each ADC are serialized and output over only one differential pair. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock by 20 to derive the bit clock that is used to serialize the 12-bit data from each channel. The devices support subclass 1 with interface speeds up to 3.2 Gbps.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	SAMPLING RATE (MSPS)
ADC34J22	VQFN (48)	50
ADC34J23		80
ADC34J24		125
ADC34J25		160

For all available packages, see the orderable addendum at the end of the datasheet.

FFT with Dither On
(f_S = 160 MSPS, f_IN= 10 MHz, SNR = 70.3 dBFS, SFDR = 84 dBc)

4 Revision History

Changes from * Revision (May 2014) to A Revision

Changed document status from product preview to production dataGo

5 Device Comparison Table

INTERFACE	RESOLUTION (Bits)	25 MSPS	50 MSPS	80 MSPS	125 MSPS	160 MSPS
Serial LVDS	12	ADC3421	ADC3422	ADC3423	ADC3424	—
Serial LVDS	14	ADC3441	ADC3442	ADC3443	ADC3444	—
JESD204B	12	—	ADC34J22	ADC34J23	ADC34J24	ADC34J25
JESD204B	14	—	ADC34J42	ADC34J43	ADC34J44	ADC34J45

6 Pin Configuration and Functions

RGZ Package

VQFN-48

(Top View)

Pin Functions

PIN		I/O	DESCRIPTION
NAME	NO.	I/O	DESCRIPTION
AVDD	4, 5, 8, 9, 12, 17, 20, 25, 28, 29, 32, 39, 46	I	Analog 1.8-V power supply
CLKM	18	I	Negative differential clock input for the ADC
CLKP	19	I	Positive differential clock input for the ADC
DAM	48	O	Negative serial JESD204B output for channel A
DAP	47	O	Positive serial JESD204B output for channel A
DBM	45	O	Negative serial JESD204B output for channel B
DBP	44	O	Positive serial JESD204B output for channel B
DCM	41	O	Negative serial JESD204B output for channel C
DCP	40	O	Positive serial JESD204B output for channel C
DDM	38	O	Negative serial JESD204B output for channel D
DDP	37	O	Positive serial JESD204B output for channel D
DVDD	3, 34	I	Digital 1.8-V power supply
GND	PowerPAD™	I	Ground, 0 V
INAM	6	I	Negative differential analog input for channel A
INAP	7	I	Positive differential analog input for channel A
INBM	11	I	Negative differential analog input for channel B
INBP	10	I	Positive differential analog input for channel B
INCM	26	I	Negative differential analog input for channel C
INCP	27	I	Positive differential analog input for channel C
INDM	31	I	Negative differential analog input for channel D
INDP	30	I	Positive differential analog input for channel D
OVRA	2	O	Overrange indicator for channel A
OVRB	1	O	Overrange indicator for channel B
OVRC	36	O	Overrange indicator for channel C
OVRD	35	O	Overrange indicator for channel D
PDN	33	I	Power-down control. This pin has an internal 150-kΩ pull-down resistor.
RESET	21	I	Hardware reset; active high. This pin has an internal 150-kΩ, pull-down resistor.
SCLK	13	I	Serial interface clock input. This pin has an internal 150-kΩ pull-down resistor.
SDATA	14	I	Serial interface data input. This pin has an internal 150-kΩ pull-down resistor.
SDOUT	16	O	Serial interface data output
SEN	15	I	Serial interface enable. Active low. This pin has an internal 150-kΩ pull-up resistor to AVDD.
SYNCM~	42	I	Negative JESD204B synch input
SYNCP~	43	I	Positive JESD204B synch input
SYSREFM	23	I	Negative external SYSREF input
SYSREFP	22	I	Positive external SYSREF input
VCM	24	O	Common-mode voltage output for the analog inputs

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

		MIN	MAX	UNIT
Supply voltage range, AVDD		–0.3	2.1	V
Supply voltage range, DVDD		–0.3	2.1	V
Voltage applied to input pins:	INAP, INBP, INCP, INDP, INAM, INBM, INCM, INDM	–0.3	Minimum (AVDD + 0.3, 2.1)	V
	CLKP, CLKM⁽²⁾	–0.3	Minimum (AVDD + 0.3, 2.1)	V
	SYSREFP, SYSREFM, SYNCP~, SYNCM~	–0.3	Minimum (AVDD + 0.3, 2.1)	V
	SCLK, SEN, SDATA, RESET, PDN	–0.3	3.6	V
Temperature	Operating free-air, T_A	–40	85	°C
	Operating junction, T_J		125	°C
	Storage, T_stg	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) When AVDD is turned off, TI recommends switching off the input clock (or ensuring the voltage on CLKP, CLKM is less than |0.3 V|). This configuration prevents the ESD protection diodes at the clock input pins from turning on.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions⁽²⁾

over operating free-air temperature range (unless otherwise noted)

			MIN	NOM	MAX	UNIT
SUPPLIES
AVDD	Analog supply voltage range		1.7	1.8	1.9	V
DVDD	Digital supply voltage range		1.7	1.8	1.9	V
ANALOG INPUT
V_ID	Differential input voltage	For input frequencies < 450 MHz		2		V_PP
V_ID	Differential input voltage	For input frequencies < 600 MHz		1		V_PP
V_IC	Input common-mode voltage		VCM ± 0.025			V
CLOCK INPUT
	Input clock frequency	Sampling clock frequency	25		160⁽¹⁾	MSPS
	Input clock amplitude (differential)	Sine wave, ac-coupled	0.2	1.5		V
		LPECL, ac-coupled		1.6		V
		LVDS, ac-coupled		0.7		V
	Input clock duty cycle		35	50	65	%
	Input clock common-mode voltage			0.95		V
DIGITAL OUTPUTS
C_LOAD	Maximum external load capacitance from each output pin to GND			3.3		pF
R_LOAD	Single-ended load resistance			100		Ω

(1) With the clock divider enabled by default for divide-by-1. Maximum sampling clock frequency for the divide-by-4 option is 640 MSPS.

(2) After power-up, to reset the device for the first time, only use the RESET pin; see the Register Initialization section.

7.4 Summary of Special Mode Registers

Table 1 lists the location, value, and functions of special mode registers in the device.

Table 1. Special Modes Summary

MODE		LOCATION	VALUE AND FUNCTION
Dither mode	DIS DITH CHA	01h [7:6], 134h[5,3]	Creates a noise floor cleaner and improves SFDR; see the Internal Dither Algorithm section. 0000 = Dither disabled 1111 = Dither enabled
	DIS DITH CHB	01h [5:4], 434h[5,3]
	DIS DITH CHC	01h [3:2], 534h[5,3]
	DIS DITH CHD	01h [1:0], 234h[5,3]
Special mode 1	SPECIAL MODE 1 CHA	06h[4:2]	Use for better HD3. 000 = Default after reset 010 = Use for frequency < 120 MHz 111 = Use for frequency > 120 MHz
	SPECIAL MODE 1 CHB	07h[4:2]
	SPECIAL MODE 1 CHC	08h[4:2]
	SPECIAL MODE 1 CHD	09h[4:2]
Special mode 2	SPECIAL MODE 2 CHA	122h[1:0]	Helps improve HD2. 00 = Default after reset 11 = Improves HD2
	SPECIAL MODE 2 CHB	422h[1:0]
	SPECIAL MODE 2 CHC	522h[1:0]
	SPECIAL MODE 2 CHD	222h[1:0]

7.5 Thermal Information

THERMAL METRIC⁽¹⁾		ADC34J2x	UNIT
		RGZ (VQFN)
		48 PINS
R_θJA	Junction-to-ambient thermal resistance	25.7	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	18.9
R_θJB	Junction-to-board thermal resistance	3.0
ψ_JT	Junction-to-top characterization parameter	0.2
ψ_JB	Junction-to-board characterization parameter	3
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	0.5

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.6 Electrical Characteristics: ADC34J24, ADC34J25

Typical values are at T_A = 25°C, full temperature range is T_MIN = –40°C to T_MAX = 85°C, maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.

PARAMETER		ADC34J24			ADC34J25			UNIT
PARAMETER		MIN	TYP	MAX	MIN	TYP	MAX	UNIT
	ADC clock frequency			125			160	MSPS
	Resolution	12			12			Bits
	1.8-V analog supply (AVDD) current		318	490		354	490	mA
	1.8-V digital supply current		79	150		97	150	mA
	Total power dissipation		715	1010		812	1010	mW
	Global power-down dissipation		22			22		mW
	Wake-up time from global power-down		85	100		85	100	µs
	Standby power-down dissipation		177			185		mW
	Wake-up time from standby power-down		35	300		35	300	µs

7.7 Electrical Characteristics: ADC34J22, ADC34J23

PARAMETER		ADC34J22			ADC34J23			UNIT
PARAMETER		MIN	TYP	MAX	MIN	TYP	MAX	UNIT
	ADC clock frequency			50			80	MSPS
	Resolution	12			12			Bits
	1.8-V analog supply current		233	490		269	490	mA
	1.8-V digital supply current		39	150		56	150	mA
	Total power dissipation		491	1010		584	1010	mW
	Global power-down dissipation		22			22		mW
	Wake-up time from global power-down		85	100		85	100	µs
	Standby power-down dissipation		155			166		mW
	Wake-up time from standby power-down		35	300		35	300	µs

7.8 Electrical Characteristics: General

Typical values are at T_A = 25°C, full temperature range is T_MIN = –40°C to T_MAX = 85°C, Maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
ANALOG INPUT
	Differential input full-scale				2.0		V_PP
r_i	Input resistance	Differential at dc			6.5		kΩ
c_i	Input capacitance	Differential at dc			5.2		pF
V_OC(VCM)	VCM common-mode voltage output				0.95		V
	VCM output current capability				10		mA
	Input common-mode current	Per analog input pin			1.5		µA/MSPS
	Analog input bandwidth (3 dB)	50-Ω differential source driving 50-Ω termination across INP and INM			450		MHz
DC ACCURACY
E_O	Offset error			–20		20	mV
E_G(REF)	Gain error as a result of internal reference inaccuracy alone			–3		3	%FS
E_G(CHAN)	Gain error of channel alone				±1		%FS
CHANNEL-TO-CHANNEL ISOLATION
	Crosstalk⁽¹⁾	f_IN = 10 MHz	Near channel		105		dB
		f_IN = 10 MHz	Far channel		105		dB
		f_IN = 100 MHz	Near channel		95		dB
		f_IN = 100 MHz	Far channel		105		dB
		f_IN = 200 MHz	Near channel		94		dB
		f_IN = 200 MHz	Far channel		105		dB
		f_IN = 230 MHz	Near channel		93		dB
		f_IN = 230 MHz	Far channel		105		dB
		f_IN = 300 MHz	Near channel		85		dB
		f_IN = 300 MHz	Far channel		105		dB

(1) Crosstalk is measured with a –1-dBFS input signal on aggressor channel and no input on victim channel.

7.9 AC Performance: ADC34J25

Typical values are at T_A = 25°C, full temperature range is T_MIN = –40°C to T_MAX = 85°C, ADC sampling rate = 160 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.

PARAMETER		TEST CONDITIONS	ADC34J25 (f_S = 160 MSPS)						UNIT
			DITHER ON			DITHER OFF
			MIN	TYP	MAX	MIN	TYP	MAX
DYNAMIC AC CHARACTERISTICS
SNR	Signal-to-noise ratio	f_IN = 10 MHz		70.2			70.4		dBFS
		f_IN = 70 MHz	68.5	69.6			69.9
		f_IN = 100 MHz		69.3			69.6
		f_IN = 170 MHz		68.4			68.9
		f_IN = 230 MHz		67.5			68.1
NSD	Noise spectral density (averaged across Nyquist zone)	f_IN = 10 MHz		149.2			149.4		dBFS/Hz
		f_IN = 70 MHz	147.5	148.6			148.9
		f_IN = 100 MHz		148.3			148.6
		f_IN = 170 MHz		147.4			147.9
		f_IN = 230 MHz		146.5			147.1
SINAD	Signal-to-noise and distortion ratio	f_IN = 10 MHz		70.1			70.3		dBFS
		f_IN = 70 MHz	67.6	69.5			69.7
		f_IN = 100 MHz		69.2			69.4
		f_IN = 170 MHz		68.2			68.6
		f_IN = 230 MHz		67.2			67.5
ENOB	Effective number of bits	f_IN = 10 MHz		11.4			11.4		Bits
		f_IN = 70 MHz	10.9	11.3			11.3
		f_IN = 100 MHz		11.2			11.3
		f_IN = 170 MHz		11.1			11.1
		f_IN = 230 MHz		10.9			10.9
SFDR	Spurious-free dynamic range	f_IN = 10 MHz		85			86		dBc
		f_IN = 70 MHz	81	86			85
		f_IN = 100 MHz		86			87
		f_IN = 170 MHz		85			84
		f_IN = 230 MHz		81			80
HD2	Second harmonic distortion	f_IN = 10 MHz		91			92		dBc
		f_IN = 70 MHz	81	94			93
		f_IN = 100 MHz		93			91
		f_IN = 170 MHz		83			83
		f_IN = 230 MHz		81			79
HD3	Third harmonic distortion	f_IN = 10 MHz		85			86		dBc
		f_IN = 70 MHz	81	85			85
		f_IN = 100 MHz		86			87
		f_IN = 170 MHz		93			87
		f_IN = 230 MHz		85			82
Non HD2, HD3	Spurious-free dynamic range (excluding HD2, HD3)	f_IN = 10 MHz		98			94		dBc
		f_IN = 70 MHz	87	97			94
		f_IN = 100 MHz		96			93
		f_IN = 170 MHz		92			92
		f_IN = 230 MHz		90			89
THD	Total harmonic distortion	f_IN = 10 MHz		84			83		dBc
		f_IN = 70 MHz	76.5	84			83
		f_IN = 100 MHz		84			84
		f_IN = 170 MHz		82			80
		f_IN = 230 MHz		78			76
IMD3	Third-order intermodulation distortion	f_IN1 = 45 MHz, f_IN2 = 50 MHz		92			92		dBFS
IMD3	Third-order intermodulation distortion	f_IN1 = 185 MHz, f_IN2 = 190 MHz		87			87		dBFS

7.10 AC Performance: ADC34J24

Typical values are at T_A = 25°C, full temperature range is T_MIN = –40°C to T_MAX = 85°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.

PARAMETER		TEST CONDITIONS	ADC34J24 (f_S = 125 MSPS)						UNIT
			DITHER ON			DITHER OFF
			MIN	TYP	MAX	MIN	TYP	MAX
DYNAMIC AC CHARACTERISTICS
SNR	Signal-to-noise ratio	f_IN = 10 MHz		70.3			70.6		dBFS
		f_IN = 70 MHz	68.8	70.1			70.4
		f_IN = 100 MHz		69.9			70.2
		f_IN = 170 MHz		69.1			69.7
		f_IN = 230 MHz		68.6			69.1
NSD	Noise spectral density (averaged across Nyquist zone)	f_IN = 10 MHz		148.3			148.6		dBFS/Hz
		f_IN = 70 MHz	146.8	148.1			148.4
		f_IN = 100 MHz		147.9			148.2
		f_IN = 170 MHz		147.1			147.7
		f_IN = 230 MHz		146.6			147.1
SINAD	Signal-to-noise and distortion ratio	f_IN = 10 MHz		70.3			70.5		dBFS
		f_IN = 70 MHz	67.6	70			70.3
		f_IN = 100 MHz		69.8			70.1
		f_IN = 170 MHz		68.9			69.3
		f_IN = 230 MHz		68.4			68.8
ENOB	Effective number of bits	f_IN = 10 MHz		11.4			11.4		Bits
		f_IN = 70 MHz	10.9	11.4			11.4
		f_IN = 100 MHz		11.3			11.4
		f_IN = 170 MHz		11.2			11.3
		f_IN = 230 MHz		11.1			11.1
SFDR	Spurious-free dynamic range	f_IN = 10 MHz		94			92		dBc
		f_IN = 70 MHz	81	93			91
		f_IN = 100 MHz		93			92
		f_IN = 170 MHz		85			83
		f_IN = 230 MHz		83			82
HD2	Second harmonic distortion	f_IN = 10 MHz		93			93		dBc
		f_IN = 70 MHz	81	94			94
		f_IN = 100 MHz		92			92
		f_IN = 170 MHz		83			83
		f_IN = 230 MHz		82			82
HD3	Third harmonic distortion	f_IN = 10 MHz		96			93		dBc
		f_IN = 70 MHz	83	94			91
		f_IN = 100 MHz		95			93
		f_IN = 170 MHz		88			86
		f_IN = 230 MHz		87			88
Non HD2, HD3	Spurious-free dynamic range (excluding HD2, HD3)	f_IN = 10 MHz		99			95		dBc
		f_IN = 70 MHz	87	98			95
		f_IN = 100 MHz		97			95
		f_IN = 170 MHz		97			92
		f_IN = 230 MHz		95			92
THD	Total harmonic distortion	f_IN = 10 MHz		89			87		dBc
		f_IN = 70 MHz	76.5	89			87
		f_IN = 100 MHz		89			87
		f_IN = 170 MHz		82			80
		f_IN = 230 MHz		81			80
IMD3	Third-order intermodulation distortion	f_IN1 = 45 MHz, f_IN2 = 50 MHz		97			97		dBFS
IMD3	Third-order intermodulation distortion	f_IN1 = 185 MHz, f_IN2 = 190 MHz		89			89		dBFS

7.11 AC Performance: ADC34J23

Typical values are at T_A = 25°C, full temperature range is T_MIN = –40°C to T_MAX = 85°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.

PARAMETER		TEST CONDITIONS	ADC34J23 (f_S = 80 MSPS)						UNIT
			DITHER ON			DITHER OFF
			MIN	TYP	MAX	MIN	TYP	MAX
DYNAMIC AC CHARACTERISTICS
SNR	Signal-to-noise ratio	f_IN = 10 MHz		70.2			70.4		dBFS
		f_IN = 70 MHz	68.7	70			70.3
		f_IN = 100 MHz		69.9			70.1
		f_IN = 170 MHz		69.3			69.6
		f_IN = 230 MHz		68.7			68.9
NSD	Noise spectral density (averaged across Nyquist zone)	f_IN = 10 MHz		146.1			146.3		dBFS/Hz
		f_IN = 70 MHz	144.8	145.9			146.2
		f_IN = 100 MHz		145.8			146.0
		f_IN = 170 MHz		145.2			145.5
		f_IN = 230 MHz		144.6			144.8
SINAD	Signal-to-noise and distortion ratio	f_IN = 10 MHz		70.2			70.3		dBFS
		f_IN = 70 MHz	67.6	70			70.2
		f_IN = 100 MHz		69.8			69.9
		f_IN = 170 MHz		69.1			69.3
		f_IN = 230 MHz		68.2			68.4
ENOB	Effective number of bits	f_IN = 10 MHz		11.4			11.4		Bits
		f_IN = 70 MHz	10.9	11.4			11.4
		f_IN = 100 MHz		11.3			11.3
		f_IN = 170 MHz		11.2			11.3
		f_IN = 230 MHz		11.1			11.1
SFDR	Spurious-free dynamic range	f_IN= 10 MHz		95			91		dBc
		f_IN = 70 MHz	82	95			90
		f_IN = 100 MHz		90			89
		f_IN = 170 MHz		87			84
		f_IN = 230 MHz		80			80
HD2	Second harmonic distortion	f_IN = 10 MHz		95			95		dBc
		f_IN = 70 MHz	82	95			94
		f_IN = 100 MHz		91			92
		f_IN = 170 MHz		83			83
		f_IN = 230 MHz		81			82
HD3	Third harmonic distortion	f_IN = 10 MHz		99			94		dBc
		f_IN = 70 MHz	83	101			94
		f_IN = 100 MHz		91			90
		f_IN = 170 MHz		92			90
		f_IN = 230 MHz		80			80
Non HD2, HD3	Spurious-free dynamic range (excluding HD2, HD3)	f_IN = 10 MHz		98			92		dBc
		f_IN = 70 MHz	87	98			92
		f_IN = 100 MHz		97			91
		f_IN = 170 MHz		96			91
		f_IN = 230 MHz		93			91
THD	Total harmonic distortion	f_IN = 10 MHz		91			86		dBc
		f_IN = 70 MHz	76.5	91			86
		f_IN = 100 MHz		87			84
		f_IN = 170 MHz		82			81
		f_IN = 230 MHz		77			77
IMD3	Third-order intermodulation distortion	f_IN1 = 45 MHz, f_IN2 = 50 MHz		95			95		dBFS
IMD3	Third-order intermodulation distortion	f_IN1 = 185 MHz, f_IN2 = 190 MHz		88			88		dBFS

7.12 AC Performance: ADC34J22

Typical values are at T_A = 25°C, full temperature range is T_MIN = –40°C to T_MAX = 85°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.

PARAMETER		TEST CONDITIONS	ADC34J22 (f_S = 50 MSPS)						UNIT
			DITHER ON			DITHER OFF
			MIN	TYP	MAX	MIN	TYP	MAX
DYNAMIC AC CHARACTERISTICS
SNR	Signal-to-noise ratio	f_IN = 10 MHz	69.3	70.2			70.5		dBFS
		f_IN = 70 MHz		70			70.3
		f_IN = 100 MHz		69.9			70.2
		f_IN = 170 MHz		69.3			69.5
		f_IN = 230 MHz		67.9			68
NSD	Noise spectral density (averaged across Nyquist zone)	f_IN = 10 MHz	143.3	144.2			144.5		dBFS/Hz
		f_IN = 70 MHz		144			144.3
		f_IN = 100 MHz		143.9			144.2
		f_IN = 170 MHz		143.3			143.5
		f_IN = 230 MHz		141.9			142
SINAD	Signal-to-noise and distortion ratio	f_IN = 10 MHz	67.6	70.2			70.4		dBFS
		f_IN = 70 MHz		69.9			70.1
		f_IN = 100 MHz		69.8			70
		f_IN = 170 MHz		69.1			69.3
		f_IN = 230 MHz		67.5			67.6
ENOB	Effective number of bits	f_IN = 10 MHz	10.9	11.4			11.4		Bits
		f_IN = 70 MHz		11.3			11.3
		f_IN = 100 MHz		11.3			11.3
		f_IN = 170 MHz		11.2			11.2
		f_IN = 230 MHz		10.9			10.9
SFDR	Spurious-free dynamic range	f_IN = 10 MHz	84.5	95			91		dBc
		f_IN = 70 MHz		93			90
		f_IN = 100 MHz		90			89
		f_IN = 170 MHz		85			84
		f_IN = 230 MHz		80			80
HD2	Second harmonic distortion	f_IN = 10 MHz	84.5	94			93		dBc
		f_IN = 70 MHz		93			93
		f_IN = 100 MHz		90			90
		f_IN = 170 MHz		83			83
		f_IN = 230 MHz		81			81
HD3	Third harmonic distortion	f_IN = 10 MHz	84.5	102			96		dBc
		f_IN = 70 MHz		94			92
		f_IN = 100 MHz		90			89
		f_IN = 170 MHz		91			90
		f_IN = 230 MHz		80			80
Non HD2, HD3	Spurious-free dynamic range (excluding HD2, HD3)	f_IN = 10 MHz	87	98			92		dBc
		f_IN = 70 MHz		97			92
		f_IN = 100 MHz		96			92
		f_IN = 170 MHz		95			91
		f_IN = 230 MHz		93			91
THD	Total harmonic distortion	f_IN = 10 MHz	76.5	91			86		dBc
		f_IN = 70 MHz		89			85
		f_IN = 100 MHz		86			84
		f_IN = 170 MHz		82			81
		f_IN = 230 MHz		77			77
IMD3	Third-order intermodulation distortion	f_IN1 = 45 MHz, f_IN2 = 50 MHz		93			93		dBFS
IMD3	Third-order intermodulation distortion	f_IN1 = 185 MHz, f_IN2 = 190 MHz		86			86		dBFS

7.13 Digital Characteristics

The dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1. AVDD = DVDD = 1.8 V and –1-dBFS differential input, unless otherwise noted.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
DIGITAL INPUTS (RESET, SCLK, SEN, SDATA, PDN)⁽¹⁾
V_IH	High-level input voltage	All digital inputs support 1.8-V and 3.3-V logic levels	1.2			V
V_IL	Low-level input voltage	All digital inputs support 1.8-V and 3.3-V logic levels			0.4	V
I_IH	High-level input current	SEN		0		µA
I_IH	High-level input current	RESET, SCLK, SDATA, PDN		10		µA
I_IL	Low-level input current	SEN		10		µA
I_IL	Low-level input current	RESET, SCLK, SDATA, PDN		0		µA
DIGITAL INPUTS (SYNCP~, SYNCM~, SYSREFP, SYSREFM)
V_IH	High-level input voltage			1.3		V
V_IL	Low-level input voltage			0.5		V
V_{(CM_DIG)}	Common-mode voltage for SYNC~ and SYSREF			0.9		V
DIGITAL OUTPUTS (SDOUT, OVRA, OVRB, OVRC, OVRD)
V_OH	High-level output voltage		DVDD – 0.1	DVDD		V
V_OL	Low-level output voltage				0.1	V
DIGITAL OUTPUTS (JESD204B Interface: DxP, DxM)⁽²⁾
V_OH	High-level output voltage			DVDD		V
V_OL	Low-level output voltage		DVDD – 0.4			V
V_OD	Output differential voltage			0.4		V
V_OC	Output common-mode voltage		DVDD – 0.2			V
	Transmitter short-circuit current	Transmitter pins shorted to any voltage between –0.25 V and 1.45 V	–100		100	mA
z_os	Single-ended output impedance			50		Ω
	Output capacitance	Output capacitance inside the device, from either output to ground		2		pF

(1) RESET, SCLK, SDATA, and PDN pins have 150-kΩ (typical) internal pull-down resistor to ground, while SEN pin has 150-kΩ (typical) pull-up resistor to AVDD.

(2) 50-Ω, single-ended external termination to 1.8 V.

7.14 Timing Characteristics

Typical values are at 25°C, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. Minimum and maximum values are across the full temperature range: T_MIN = –40°C to T_MAX = 85°C. See Figure 143.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SAMPLE TIMING CHARACTERISTICS
	Aperture delay		0.85	1.25	1.65	ns
	Aperture delay matching	Between two channels on the same device		±70		ps
	Aperture delay matching	Between two devices at the same temperature and supply voltage		±150		ps
	Aperture jitter			200		f_S rms
	Wake-up time	Time to valid data after coming out of STANDBY mode		35	100	µs
	Wake-up time	Time to valid data after coming out of global power-down		85	300	µs
t_{SU_SYNC~}	Setup time for SYNC~	Referenced to input clock rising edge	1			ns
t_{H_SYNC~}	Hold time for SYNC~	Referenced to input clock rising edge	100			ps
t_{SU_SYSREF}	Setup time for SYSREF	Referenced to input clock rising edge	1			ns
t_{H_SYSREF}	Hold time for SYSREF	Referenced to input clock rising edge	100			ps
CML OUTPUT TIMING CHARACTERISTICS
	Unit interval		312.5		1667	ps
	Serial output data rate				3.2	Gbps
	Total jitter	3.125 Gbps (20x mode, f_S = 156.25 MSPS)		0.3		_P-PUI
t_R, t_F	Data rise time, data fall time	Rise and fall times measured from 20% to 80%, differential output waveform, 600 Mbps ≤ bit rate ≤ 3.125 Gbps		105		ps

Table 2. Latency in Different Modes⁽¹⁾⁽²⁾

MODE	PARAMETER	LATENCY (N Cycles)	TYPICAL DATA DELAY (t_D, ns)
20x	ADC latency	17	0.29 × t_S + 3
	Normal OVR latency	9	0.5 × t_S + 2
	Fast OVR latency	7	0.5 × t_S + 2
	From SYNC~ falling edge to CGS phase⁽³⁾	15	0.3 × t_S + 4
	From SYNC~ rising edge to ILA sequence⁽⁴⁾	17	0.3 × t_S + 4
40x	ADC latency	16	0.85 × t_S + 3.9
	Normal OVR latency	9	0.5 × t_S + 2
	Fast OVR latency	7	0.5 × t_S + 2
	From SYNC~ falling edge to CGS phase⁽³⁾	14	0.9 × t_S + 4
	From SYNC~ rising edge to ILA sequence⁽⁴⁾	12	0.9 × t_S + 4

(1) Overall latency = latency + t_D.

(2) t_S is the time period of the ADC conversion clock.

(3) Latency is specified for subclass 2. In subclass 0, the SYNC~ falling edge to CGS phase latency is 16 clock cycles in 10x mode and 15 clock cycles in 20x mode.

(4) Latency is specified for subclass 2. In subclass 0, the SYNC~ rising edge to ILA sequence latency is 11 clock cycles in 10x mode and 11 clock cycles in 20x mode.

7.15 Typical Characteristics: ADC34J25

Typical values are at T_A = 25°C, ADC sampling rate = 160 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-V_PP full-scale, 32k-point FFT, dither enabled, and special modes written, unless otherwise noted.

f_S = 160 MSPS, SNR = 70.3 dBFS, f_IN = 10 MHz, SFDR = 84 dBc

Figure 1. FFT for 10-MHz Input Signal (Dither On)

f_S = 160 MSPS, SNR = 69.7 dBFS, f_IN = 70 MHz, SFDR = 86 dBc

Figure 3. FFT for 70-MHz Input Signal (Dither On)

f_S = 160 MSPS, SNR = 67.9 dBFS, f_IN = 170 MHz,
SFDR = 84.1 dBc

Figure 5. FFT for 170-MHz Input Signal (Dither On)

f_S = 160 MSPS, SNR = 67.0 dBFS, f_IN = 270 MHz,
SFDR = 76.2 dBc

Figure 7. FFT for 270-MHz Input Signal (Dither On)

f_S = 160 MSPS, SNR = 62.9 dBFS, f_IN = 450 MHz,
SFDR = 67.8 dBc

Figure 9. FFT for 450-MHz Input Signal (Dither On)

f_S = 160 MSPS, IMD = 92 dBFS, f_IN1 = 46 MHz, f_IN2 = 50 MHz, SFDR = 96 dBFS

Figure 11. FFT for Two-Tone Input Signal
(–7 dBFS at 46 MHz and 50 MHz)

f_S = 160 MSPS, IMD = 87 dBFS, f_IN1 = 185 MHz, f_IN2 = 190 MHz, SFDR = 90 dBFS

Figure 13. FFT for Two-Tone Input Signal
(–7 dBFS at 185 MHz and 190 MHz)

Figure 15. Intermodulation Distortion vs Input Amplitude
(46 MHz and 50 MHz)

Figure 17. Signal-to-Noise Ratio vs Input Frequency

Figure 19. Signal-to-Noise Ratio vs
Digital Gain and Input Frequency

Figure 21. Performance vs Input Amplitude
(30 MHz)

Figure 23. Performance vs Input Common-Mode Voltage
(30 MHz)

Figure 25. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature

Figure 27. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature

Figure 29. Performance vs Clock Amplitude
(40 MHz)

Figure 31. Performance vs Clock Duty Cycle
(40 MHz)

RMS noise = 1.3 LSBs

Figure 33. Idle Channel Histogram

f_S = 160 MSPS, SNR = 70.7 dBFS, f_IN = 10 MHz,
SFDR = 81.1 dBc

Figure 2. FFT for 10-MHz Input Signal (Dither Off)

f_S = 160 MSPS, SNR = 70.1 dBFS, f_IN = 70 MHz,
SFDR = 87.5 dBc

Figure 4. FFT for 70-MHz Input Signal (Dither Off)

f_S = 160 MSPS, SNR = 68.1 dBFS, f_IN = 70 MHz,
SFDR = 82.7 dBc

Figure 6. FFT for 170-MHz Input Signal (Dither Off)

f_S = 160 MSPS, SNR = 67.5 dBFS, f_IN = 270 MHz,
SFDR = 75.9 dBc

Figure 8. FFT for 270-MHz Input Signal (Dither Off)

f_S = 160 MSPS, SNR = 63.6 dBFS, f_IN = 450 MHz,
SFDR = 67.6 dBc

Figure 10. FFT for 450-MHz Input Signal (Dither Off)

f_S = 160 MSPS, IMD = 98 dBFS, f_IN1 = 46 MHz, f_IN2 = 50 MHz, SFDR = 102 dBFS

Figure 12. FFT for Two-Tone Input Signal
(–36 dBFS at 46 MHz and 50 MHz)

f_S = 160 MSPS, IMD = 98 dBFS, f_IN1 = 185 MHz, f_IN2 = 190 MHz, SFDR = 102 dBFS

Figure 14. FFT for Two-Tone Input Signal
(–36 dBFS at 185 MHz and 190 MHz)

Figure 16. Intermodulation Distortion vs Input Amplitude
(185 MHz and 190 MHz)

Figure 18. Spurious-Free Dynamic Range vs
Input Frequency

Figure 20. Spurious-Free Dynamic Range vs
Digital Gain and Input Frequency

Figure 22. Performance vs Input Amplitude
(170 MHz)

Figure 24. Performance vs Input Common-Mode Voltage (170 MHz)

Figure 26. Signal-to-Noise Ratio vs
AVDD Supply and Temperature

Figure 28. Signal-to-Noise Ratio vs
DVDD Supply and Temperature

Figure 30. Performance vs Clock Amplitude
(150 MHz)

Figure 32. Performance vs Clock Duty Cycle
(150 MHz)

7.16 Typical Characteristics: ADC34J24

Typical values are at T_A = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-V_PP full-scale, and 32k-point FFT, unless otherwise noted.

f_S = 125 MSPS, SNR = 70.3 dBFS, f_IN = 10 MHz,
SFDR = 91.3 dBc

Figure 34. FFT for 10-MHz Input Signal (Dither On)

f_S = 125 MSPS, SNR = 70 dBFS, f_IN = 70 MHz, SFDR = 93.5 dBc

Figure 36. FFT for 70-MHz Input Signal (Dither On)

f_S = 125 MSPS, SNR = 69 dBFS, f_IN = 170 MHz,
SFDR = 85.9 dBc

Figure 38. FFT for 170-MHz Input Signal (Dither On)

f_S = 125 MSPS, SNR = 68.4 dBFS, f_IN = 270 MHz,
SFDR = 79.8 dBc

Figure 40. FFT for 270-MHz Input Signal (Dither On)

f_S = 125 MSPS, SNR = 65.2 dBFS, f_IN = 450 MHz,
SFDR = 62.9 dBc

Figure 42. FFT for 450-MHz Input Signal (Dither On)

f_S = 125 MSPS, IMD = 93 dBFS, f_IN1 = 46 MHz, f_IN2 = 50 MHz, SFDR = 97 dBFS

Figure 44. FFT for Two-Tone Input Signal
(–7dBFS at 46 MHz and 50 MHz)

f_S = 125 MSPS, IMD = 89 dBFS, f_IN1 = 185 MHz, f_IN2 = 190 MHz, SFDR = 92 dBFS

Figure 46. FFT for Two-Tone Input Signal
(–7 dBFS at 185 MHz and 190 MHz)

Figure 48. Intermodulation Distortion vs Input Amplitude
(46 MHz and 50 MHz)

Figure 50. Signal-to-Noise Ratio vs Input Frequency

Figure 52. Signal-to-Noise Ratio vs
Digital Gain and Input Frequency

Figure 54. Performance vs Input Amplitude
(30 MHz)

Figure 56. Performance vs Input Common-Mode Voltage
(30 MHz)

Figure 58. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature

Figure 60. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature

Figure 62. Performance vs Clock Amplitude
(40 MHz)

Figure 64. Performance vs Clock Duty Cycle
(40 MHz)

RMS noise = 1.4 LSBs

Figure 66. Idle Channel Histogram

f_S = 125 MSPS, SNR = 70.5 dBFS, f_IN = 10 MHz,
SFDR = 90.9 dBc

Figure 35. FFT for 10-MHz Input Signal (Dither Off)

f_S = 125 MSPS, SNR = 70.3 dBFS, f_IN = 70 MHz,
SFDR = 94.3 dBc

Figure 37. FFT for 70-MHz Input Signal (Dither Off)

f_S = 125 MSPS, SNR = 69.6 dBFS, f_IN = 70 MHz,
SFDR = 86.5 dBc

Figure 39. FFT for 170-MHz Input Signal (Dither Off)

f_S = 125 MSPS, SNR = 68.8 dBFS, f_IN = 270 MHz,
SFDR = 79.6 dBc

Figure 41. FFT for 270-MHz Input Signal (Dither Off)

f_S = 125 MSPS, SNR = 66.1 dBFS, f_IN = 450 MHz,
SFDR = 63.1 dBc

Figure 43. FFT for 450-MHz Input Signal (Dither Off)

f_S = 125 MSPS, IMD = 101 dBFS, f_IN1 = 46 MHz, f_IN2 = 50 MHz, SFDR = 106 dBFS

Figure 45. FFT for Two-Tone Input Signal
(–36 dBFS at 46 MHz and 50 MHz)

f_S = 125 MSPS, IMD = 99 dBFS, f_IN1 = 185 MHz, f_IN2 = 190 MHz, SFDR = 103 dBFS

Figure 47. FFT for Two-Tone Input Signal
(–36 dBFS at 185 MHz and 190 MHz)

Figure 49. Intermodulation Distortion vs Input Amplitude
(185 MHz and 190 MHz)

Figure 51. Spurious-Free Dynamic Range vs
Input Frequency

Figure 53. Spurious-Free Dynamic Range vs
Digital Gain and Input Frequency

Figure 55. Performance vs Input Amplitude
(170 MHz)

Figure 57. Performance vs Input Common-Mode Voltage (170 MHz)

Figure 59. Signal-to-Noise Ratio vs
AVDD Supply and Temperature

Figure 61. Signal-to-Noise Ratio vs
DVDD Supply and Temperature

Figure 63. Performance vs Clock Amplitude
(150 MHz)

Figure 65. Performance vs Clock Duty Cycle
(150 MHz)

7.17 Typical Characteristics: ADC34J23

Typical values are at T_A = 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-V_PP full-scale, and 32k-point FFT, unless otherwise noted.

f_S = 80 MSPS, SNR = 70.3 dBFS, f_IN = 10 MHz, SFDR = 96.6 dBc

Figure 67. FFT for 10-MHz Input Signal (Dither On)

f_S = 80 MSPS, SNR = 70 dBFS, f_IN = 70 MHz, SFDR = 99.5 dBc

Figure 69. FFT for 70-MHz Input Signal (Dither On)

f_S = 80 MSPS, SNR = 69.3 dBFS, f_IN = 170 MHz,
SFDR = 92.7 dBc

Figure 71. FFT for 170-MHz Input Signal (Dither On)

f_S = 80 MSPS, SNR = 68.4 dBFS, f_IN = 270 MHz,
SFDR = 76.4 dBc

Figure 73. FFT for 270-MHz Input Signal (Dither On)

f_S = 80 MSPS, SNR = 65.5 dBFS, f_IN = 450 MHz,
SFDR = 63.3 dBc

Figure 75. FFT for 450-MHz Input Signal (Dither On)

f_S = 80 MSPS, IMD = 95 dBFS, f_IN1 = 46 MHz, f_IN2 = 50 MHz, SFDR = 99 dBFS

Figure 77. FFT for Two-Tone Input Signal
(–7 dBFS at 46 MHz and 50 MHz)

f_S = 80 MSPS, IMD = 88 dBFS, f_IN1 = 185 MHz, f_IN2 = 190 MHz, SFDR = 94 dBFS

Figure 79. FFT for Two-Tone Input Signal
(–7 dBFS at 185 MHz and 190 MHz)

Figure 81. Intermodulation Distortion vs Input Amplitude
(46 MHz and 50 MHz)

Figure 83. Signal-to-Noise Ratio vs Input Frequency

Figure 85. Signal-to-Noise Ratio vs
Digital Gain and Input Frequency

Figure 87. Performance vs Input Amplitude
(30 MHz)

Figure 89. Performance vs Input Common-Mode Voltage
(30 MHz)

Figure 91. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature

Figure 93. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature

Figure 95. Performance vs Clock Amplitude
(40 MHz)

Figure 97. Performance vs Clock Duty Cycle
(40 MHz)

RMS noise = 1.4 LSBs

Figure 99. Idle Channel Histogram

f_S = 80 MSPS, SNR = 70.6 dBFS, f_IN = 10 MHz, SFDR = 90.3 dBc

Figure 68. FFT for 10-MHz Input Signal (Dither Off)

f_S = 80 MSPS, SNR = 70.4 dBFS, f_IN = 70 MHz, SFDR = 90.1 dBc

Figure 70. FFT for 70-MHz Input Signal (Dither Off)

f_S = 80 MSPS, SNR = 69.6 dBFS, f_IN = 10 MHz, SFDR = 92.9 dBc

Figure 72. FFT for 170-MHz Input Signal (Dither Off)

f_S = 80 MSPS, SNR = 68.3 dBFS, f_IN = 270 MHz,
SFDR = 76.9 dBc

Figure 74. FFT for 270-MHz Input Signal (Dither Off)

f_S = 80 MSPS, SNR = 66.2 dBFS, f_IN = 450 MHz,
SFDR = 62.9 dBc

Figure 76. FFT for 450-MHz Input Signal (Dither Off)

f_S = 80 MSPS, IMD = 101 dBFS, f_IN1 = 46 MHz, f_IN2 = 50 MHz, SFDR = 106 dBFS

Figure 78. FFT for Two-Tone Input Signal
(–36 dBFS at 46 MHz and 50 MHz)

f_S = 80 MSPS, IMD = 100 dBFS, f_IN1 = 185 MHz, f_IN2 = 190 MHz, SFDR = 102 dBFS

Figure 80. FFT for Two-Tone Input Signal
(–36 dBFS at 185 MHz and 190 MHz)

Figure 82. Intermodulation Distortion vs Input Amplitude
(185 MHz and 190 MHz)

Figure 84. Spurious-Free Dynamic Range vs
Input Frequency

Figure 86. Spurious-Free Dynamic Range vs
Digital Gain and Input Frequency

Figure 88. Performance vs Input Amplitude
(170 MHz)

Figure 90. Performance vs Input Common-Mode Voltage (170 MHz)

Figure 92. Signal-to-Noise Ratio vs
AVDD Supply and Temperature

Figure 94. Signal-to-Noise Ratio vs
DVDD Supply and Temperature

Figure 96. Performance vs Clock Amplitude
(150 MHz)

Figure 98. Performance vs Clock Duty Cycle
(150 MHz)

7.18 Typical Characteristics: ADC34J22

Typical values are at T_A = 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-V_PP full-scale, and 32k-point FFT, unless otherwise noted.

f_S = 50 MSPS, SNR = 70.2 dBFS, f_IN = 10 MHz, SFDR = 96.5 dBc

Figure 100. FFT for 10-MHz Input Signal (Dither On)

f_S = 50 MSPS, SNR = 69.9 dBFS, f_IN = 70 MHz, SFDR = 92.6 dBc

Figure 102. FFT for 70-MHz Input Signal (Dither On)

f_S = 50 MSPS, SNR = 69.3 dBFS, f_IN = 170 MHz,
SFDR = 88.7 dBc

Figure 104. FFT for 170-MHz Input Signal (Dither On)

f_S = 50 MSPS, SNR = 68.3 dBFS, f_IN = 270 MHz,
SFDR = 76.9 dBc

Figure 106. FFT for 270-MHz Input Signal (Dither On)

f_S = 50 MSPS, SNR = 66.1 dBFS, f_IN = 450 MHz,
SFDR = 63.1 dBc

Figure 108. FFT for 450-MHz Input Signal (Dither On)

f_S = 50 MSPS, IMD = 93 dBFS, f_IN1 = 46 MHz, f_IN2 = 50 MHz, SFDR = 96 dBFS

Figure 110. FFT for Two-Tone Input Signal
(–7dBFS at 46 MHz and 50 MHz)

f_S = 50 MSPS, IMD = 86 dBFS, f_IN1 = 185 MHz, f_IN2 = 190 MHz, SFDR = 92 dBFS

Figure 112. FFT for Two-Tone Input Signal
(–7 dBFS at 185 MHz and 190 MHz)

Figure 114. Intermodulation Distortion vs Input Amplitude
(46 MHz and 50 MHz)

Figure 116. Signal-to-Noise Ratio vs Input Frequency

Figure 118. Signal-to-Noise Ratio vs
Digital Gain and Input Frequency

Figure 120. Performance vs Input Amplitude
(30 MHz)

Figure 122. Performance vs Input Common-Mode Voltage (30 MHz)

Figure 124. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature

Figure 126. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature

Figure 128. Performance vs Clock Amplitude
(40 MHz)

Figure 130. Performance vs Clock Duty Cycle
(40 MHz)

RMS noise = 1.3 LSBs

Figure 132. Idle Channel Histogram

f_S = 50 MSPS, SNR = 70.6 dBFS, f_IN = 10 MHz, SFDR = 90.4 dBc

Figure 101. FFT for 10-MHz Input Signal (Dither Off)

f_S = 50 MSPS, SNR = 70.3 dBFS, f_IN = 70 MHz, SFDR = 88 dBc

Figure 103. FFT for 70-MHz Input Signal (Dither Off)

f_S = 50 MSPS, SNR = 69.5 dBFS, f_IN = 170 MHz,
SFDR = 88.5 dBc

Figure 105. FFT for 170-MHz Input Signal (Dither Off)

f_S = 50 MSPS, SNR = 68.4 dBFS, f_IN = 270 MHz,
SFDR = 76.5 dBc

Figure 107. FFT for 270-MHz Input Signal (Dither Off)

f_S = 50 MSPS, SNR = 66.3 dBFS, f_IN = 450 MHz,
SFDR = 63.2 dBc

Figure 109. FFT for 450-MHz Input Signal (Dither Off)

f_S = 50 MSPS, IMD = 99 dBFS, f_IN1 = 46 MHz, f_IN2 = 50 MHz, SFDR = 106 dBFs

Figure 111. FFT for Two-Tone Input Signal
(–36 dBFS at 46 MHz and 50 MHz)

f_S = 50 MSPS, IMD = 99 dBFS, f_IN1 = 185 MHz, f_IN2 = 190 MHz, SFDR = 102 dBFs

Figure 113. FFT for Two-Tone Input Signal
(–36 dBFS at 185 MHz and 190 MHz)

Figure 115. Intermodulation Distortion vs Input Amplitude
(185 MHz and 190 MHz)

Figure 117. Spurious-Free Dynamic Range vs
Input Frequency

Figure 119. Spurious-Free Dynamic Range vs
Digital Gain and Input Frequency

Figure 121. Performance vs Input Amplitude
(170 MHz)

Figure 123. Performance vs Input Common-Mode Voltage (170 MHz)

Figure 125. Signal-to-Noise Ratio vs
AVDD Supply and Temperature

Figure 127. Signal-to-Noise Ratio vs
DVDD Supply and Temperature

Figure 129. Performance vs Clock Amplitude
(150 MHz)

Figure 131. Performance vs Clock Duty Cycle
(150 MHz)

7.19 Typical Characteristics: Common Plots

Typical values are at T_A = 25°C, ADC sampling rate = 160 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-V_PP full-scale, and 32k-point FFT, unless otherwise noted.

f_S = 160 MSPS, f_CM = 10 MHz, 50 mV_PP, f_IN = 30 MHz, Amplitude (f_IN + f_CM ) = –98 dBFS, Amplitude (f_IN – f_CM ) = –91 dBFS

Figure 133. Common-Mode Rejection Ratio FFT

f_S = 160 MSPS, f_PSRR = 5 MHz, 50 mV_PP, f_IN = 30 MHz, Amplitude (f_IN + f_PSRR ) = –62 dBFS, Amplitude (f_IN – f_PSRR ) = –65.35 dBFS

Figure 135. Power-Supply Rejection Ratio FFT for
AVDD Supply

Figure 137. Power vs Sampling Frequency
(20x Mode)

Input frequency = 30 MHz, 50-mV_PP signal superimposed on VCM

Figure 134. Common-Mode Rejection Ratio vs
Test Signal Frequency

Input frequency = 30 MHz, 50-mV_PP signal superimposed on VCM

Figure 136. Power-Supply Rejection Ratio vs
Test Signal Frequency

Figure 138. Power vs Sampling Frequency
(40x Mode)

7.20 Typical Characteristics: Contour Plots

Typical values are at T_A = 25°C, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-V_PP full-scale, and 32k-point FFT, unless otherwise noted.

Figure 139. Spurious-Free Dynamic Range (SFDR) for 0-dB Gain

Figure 140. Spurious-Free Dynamic Range (SFDR) for 6-dB Gain

Figure 141. Signal-to-Noise Ratio (SNR) for 0-dB Gain

Figure 142. Signal-to-Noise Ratio (SNR) for 6-dB Gain