The ADS41Bx9 are members of the ultralow-power ADS4xxx analog-to-digital converter (ADC) family, featuring integrated analog input buffers. These devices use innovative design techniques to achieve high dynamic performance, and consume extremely low power. The analog input pins have buffers, with benefits of constant performance and input impedance across a wide frequency range. The devices are well-suited for multi-carrier, wide bandwidth communications applications such as PA linearization.
The ADS41Bx9 have features such as digital gain and offset correction. The gain option can be used to improve SFDR performance at lower full-scale input ranges, especially at high input frequencies. The integrated dc offset correction loop can be used to estimate and cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled-down power with no loss in performance.
The devices support both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel CMOS digital output interfaces. The low data rate of the DDR LVDS interface (maximum 500 MBPS) makes using low-cost field-programmable gate array (FPGA)-based receivers possible. The devices have a low-swing LVDS mode that can be used to further reduce the power consumption. The strength of the LVDS output buffers can also be increased to support 50-Ω differential termination.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
ADS41Bx9 | VQFN (48) | 7.00 mm × 7.00 mm |
Changes from E Revision (July 2012) to F Revision
Changes from D Revision (December 2010) to E Revision
NOINDENT:
The PowerPAD is connected to DRGND.PIN | NO. | I/O | DESCRIPTION | |
---|---|---|---|---|
NAME | ADS41B49 | ADS41B29 | ||
AGND | 9, 12, 14, 17, 19, 25 | 9, 12, 14, 17, 19, 25 | I | Analog ground |
AVDD | 8, 18, 20, 22, 24, 26 | 8, 18, 20, 22, 24, 26 | I | 1.8-V analog power supply |
AVDD_BUF | 21 | 21 | I | 3.3-V input buffer supply |
CLKM | 11 | 11 | I | Differential clock input, negative |
CLKP | 10 | 10 | I | Differential clock input, positive |
CLKOUTP | 5 | 5 | O | Differential output clock, true |
CLKOUTM | 4 | 4 | O | Differential output clock, complement |
D0_D1_M | 33 | 37 | O | Differential output data D0 and D1 multiplexed, complement |
D0_D1_P | 34 | 38 | O | Differential output data D0 and D1 multiplexed, true |
D2_D3_M | 37 | 39 | O | Differential output data D2 and D3 multiplexed, complement |
D2_D3_P | 38 | 40 | O | Differential output data D2 and D3 multiplexed, true |
D4_D5_M | 39 | 41 | O | Differential output data D4 and D5 multiplexed, complement |
D4_D5_P | 40 | 42 | O | Differential output data D4 and D5 multiplexed, true |
D6_D7_M | 41 | 43 | O | Differential output data D6 and D7 multiplexed, complement |
D6_D7_P | 42 | 44 | O | Differential output data D6 and D7 multiplexed, true |
D8_D9_M | 43 | 45 | O | Differential output data D8 and D9 multiplexed, complement |
D8_D9_P | 44 | 46 | O | Differential output data D8 and D9 multiplexed, true |
D10_D11_M | 45 | 47 | O | Differential output data D10 and D11 multiplexed, complement |
D10_D11_P | 46 | 48 | O | Differential output data D10 and D11 multiplexed, true |
D12_D13_M | 47 | — | O | Differential output data D12 and D13 multiplexed, complement |
D12_D13_P | 48 | — | O | Differential output data D12 and D13 multiplexed, true |
DFS | 6 | 6 | I | Data format select input. This pin sets the DATA FORMAT (twos complement or offset binary) and the LVDS, CMOS output interface type. |
DRGND | 1, 36 | 1, 36 | I | Digital and output buffer ground |
DRVDD | 2, 35 | 2, 35 | I | 1.8-V digital and output buffer supply |
INM | 16 | 16 | I | Differential analog input, negative |
INP | 15 | 15 | I | Differential analog input, positive |
NC | 31, 32 | 31-34 | — | Do not connect |
OE | 7 | 7 | I | Output buffer enable input, active high; this pin has an internal 100-kΩ pull-up resistor to DRVDD. |
OVR_SDOUT | 3 | 3 | O | This pin functions as an out-of-range indicator after reset, when register bit READOUT = 0, and functions as a serial register readout pin when READOUT = 1. This pin is a 1.8-V CMOS output pin (running off of DRVDD). |
RESERVED | 23 | 23 | I | Digital control pin, reserved for future use |
RESET | 30 | 30 | I | Serial interface RESET input. When using the serial interface mode, the internal registers must initialize through hardware RESET by applying a high pulse on this pin or by using the software reset option; see the Serial Interface section. When RESET is tied high, the internal registers are reset to the default values. In this condition, SDATA can be used as a control pin. RESET has an internal 100-kΩ pull-down resistor. |
SCLK | 29 | 29 | I | This pin functions as a serial interface clock input when RESET is low. When RESET is high, SCLK has no function and must be tied to ground. This pin has an internal 180-kΩ pull-down resistor |
SDATA | 28 | 28 | I | This pin functions as a serial interface data input when RESET is low. When RESET is high, SDATA functions as a STANDBY control pin (see Table 7). This pin has an internal 180-kΩ pull-down resistor. |
SEN | 27 | 27 | I | This pin functions as a serial interface enable input when RESET is low. When RESET is high, SEN has no function and must be tied to AVDD. This pin has an internal 180-kΩ pull-up resistor to AVDD. |
VCM | 13 | 13 | O | Outputs the common-mode voltage that can be used externally to bias the analog input pins. |