ADS42LBx9 14- and 16-Bit, 250-MSPS, Analog-to-Digital Converters
- SLAS904F October 2012 – May 2016 ADS42LB49 , ADS42LB69
  
  PRODUCTION DATA.

Full reading width

DATA SHEET

ADS42LBx9 14- and 16-Bit, 250-MSPS, Analog-to-Digital Converters

1 Features

Dual Channel
14- and 16-Bit Resolution
Maximum Clock Rate: 250 MSPS
Analog Input Buffer with High Impedance Input
Flexible Input Clock Buffer with
Divide-by-1, -2, and -4
2-V_PP and 2.5-V_PP Differential Full-Scale Input (SPI-Programmable)
DDR or QDR LVDS Interface
64-Pin VQFN Package (9-mm × 9-mm)
Power Dissipation: 820 mW/ch
Aperture Jitter: 85 f_S
Internal Dither
Channel Isolation: 100 dB
Performance at f_IN = 170 MHz at 2 V_PP, –1 dBFS
- SNR: 73.2 dBFS
- SFDR:
  - 87 dBc (HD2 and HD3)
  - 100 dBc (Non HD2 and HD3)
Performance at f_IN = 170 MHz:
2.5 V_PP, –1 dBFS
- SNR: 74.9 dBFS
- SFDR:
  - 85 dBc (HD2 and HD3)
  - 97 dBc (Non HD2 and HD3)

2 Applications

Communication and Cable Infrastructure
Multi-Carrier, Multimode Cellular Receivers
Radar and Smart Antenna Arrays
Broadband Wireless
Test and Measurement Systems
Software-Defined and Diversity Radios
Microwave and Dual-Channel I/Q Receivers
Repeaters
Power Amplifier Linearization

3 Description

The ADS42LB49 and ADS42LB69 are a family of high-linearity, dual-channel, 14- and 16-bit,
250-MSPS, analog-to-digital converters (ADCs) supporting DDR and QDR LVDS output interfaces. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy. A sampling clock divider allows more flexibility for system clock architecture design. The ADS42LBx9 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with low-power consumption.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	INTERFACE OPTION
ADS42LB49	VQFN (64)	14-bit DDR or QDR LVDS
ADS42LB49	VQFN (64)	14-bit JESD204B
ADS42LB69	VQFN (64)	16-bit DDR or QDR LVDS
ADS42LB69	VQFN (64)	16-bit JESD204B

For all available packages, see the orderable addendum at the end of the datasheet.

space

Simplified Schematic

ADS42LB49 ADS42LB69 fbd_2x_ddr_las904.gif

4 Revision History

Changes from E Revision (December 2014) to F Revision

Added Using the ADS42LBx9 In Time-Domain, Low-Frequency Pulse Applications sectionGo
Added Community Resources section Go

Changes from D Revision (September 2013) to E Revision

Added ESD Ratings table and Feature Description, Device Functional Modes, Application and Implementation, Power Supply Recommendations, Layout, Device and Documentation Support, and Mechanical, Packaging, and Orderable Information sectionsGo
Deleted Ordering Information sectionGo
Merged all Pin Functions tables into one tableGo
Changed INAP, INAM pin numbers for ADS42LB69 and ADS42LB49 DDR LVDS in pin assignments tableGo
Added footnote to Table 1 Go
Added footnote to Table 2 Go
Changed pin 34 to pin 37 in Figure 79 Go

Changes from C Revision (September 2013) to D Revision

Changed device status to Production DataGo
Added pre-RTM changes throughout documentGo

Changes from B Revision (March 2013) to C Revision

Added pre-RTM changes throughout documentGo

Changes from A Revision (November 2012) to B Revision

Added pre-RTM changes throughout documentGo

Changes from * Revision (October 2012) to A Revision

Added pre-RTM changes throughout documentGo

5 Pin Configuration and Functions

ADS42LB69 DDR LVDS: RGC Package

64-Pin VQFN

Top View

ADS42LB49 ADS42LB69 po_42lb69_las904.gif

ADS42LB49 DDR LVDS: RGC Package

64-Pin VQFN

Top View

ADS42LB49 ADS42LB69 po_42lb49_las904.gif

ADS42LB69, ADS42LB49 QDR LVDS: RGC Package

64-Pin VQFN

Top View

ADS42LB49 ADS42LB69 po_2x_ddr_las904.gif

Pin Functions

PIN				I/O	DESCRIPTION
NAME	ADS42LB69 DDR LVDS	ADS42LB49 DDR LVDS	QDR LVDS	I/O	DESCRIPTION
INPUT AND REFERENCE
INAP, INAM	35, 34	35, 34	34, 35	I	Differential analog input for channel A
INBP, INBM	14, 15	14, 15	14, 15	I	Differential analog input for channel B
VCM	27	27	27	O	Common-mode voltage for analog inputs, 1.9 V
CLOCK AND SYNC
CLKINP, CLKINM	25, 24	25, 24	24, 25	I	Differential clock input for ADC
SYNCINP, SYNCINM	29, 30	29, 30	29, 30	I	External sync input. If not used, connect SYNCINP to GND and SYNCINM to AVDD.
CONTROL AND SERIAL
CTRL1	37	37	37	I/O	Can be configured as power-down input pin or as OVR output pin for channel A, depending on the register bit PDN/OVR FOR CTRL PINS.
CTRL2	12	12	12	I/O	Can be configured as power-down input pin or as OVR output pin for channel B, depending on the register bit PDN/OVR FOR CTRL PINS
NC	—	—	39, 40, 55-58, 60, 61	—	Do not connect
NC/OVR	—	9, 10, 39, 40	—	—	If the OVR ON LSB bit is set, these pins can be used because they carry overrange information. Otherwise, do not connect these pins.
Reserved	28	28	28	—	Do not connect
RESET	22	22	22	I	Hardware reset. Active high.
SCLK	18	18	18	I	Serial interface clock input
SDATA	19	19	19	I	Serial interface data input
SDOUT	21	21	21	O	Serial interface data output
SEN	20	20	20	I	Serial interface enable
DATA INTERFACE
CLKOUTP, CLKOUTM	57, 56	57, 56	—	O	Differential LVDS output clock
DA[3:0]P, DA[3:0]M	—	—	41-44, 47, 48, 50, 51	O	4-bit QDR LVDS output interface for channel A
DA[14:0]P, DA[14:0]M	39-48, 50-55	41-48, 50-55	—	O	DDR LVDS output interface for channel A
DACLKP, DACLKM	—	—	45, 46	O	Differential output clock for channel A
DAFRAMEP, DAFRAMEM	—	—	52, 53	—	Differential frame clock output for channel A
DB[3:0]P, DB[3:0]M	—	—	1, 2, 5-8, 62, 63	—	4-bit QDR LVDS output interface for channel B
DB[14:0]P, DB[14:0]M	1-10, 58-63	1-8, 58-63	—	O	DDR LVDS output interface for channel B
DBCLKP, DBCLKM	—	—	3, 4	—	Differential output clock for channel A
DBFRAMEP, DBFRAMEM	—	—	9, 10	—	Differential frame clock output for channel A
OVRA	—	—	54	O	Overrange indication channel A
OVRB	—	—	59	O	Overrange indication channel A
POWER SUPPLY
AVDD	13, 16, 23, 26, 31, 33, 36, 38	13, 16, 23, 26, 31, 33, 36, 38	13, 16, 23, 26, 31, 33, 36, 38	I	Analog 1.8-V power supply
AVDD3V	17, 32	17, 32	17, 32	I	Analog 3.3 V power supply for analog buffer
DRVDD	11, 49, 64	11, 49, 64	11, 49, 64	I	Digital 1.8-V power supply
GND	Ground pad	Ground pad	Ground pad	I	Ground

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Supply voltage	AVDD3V	–0.3	3.6	V
	AVDD	–0.3	2.1
	DRVDD	–0.3	2.1
Voltage between AGND and DGND		–0.3	0.3	V
Voltage applied to input pins	INA, INBP, INA, INBM	–0.3	3	V
	CLKINP, CLKINM	–0.3	AVDD + 0.3
	SYNCINP, SYNCINM	–0.3	AVDD + 0.3
	SCLK, SEN, SDATA, RESET, CTRL1, CTRL2	–0.3	3.9
Temperature	Operating free-air, T_A	–40	+85	°C
	Operating junction, T_J		+125
	Storage, T_stg	–65	+150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)⁽³⁾

			MIN	NOM	MAX	UNIT
SUPPLIES
AVDD	Analog supply voltage		1.7	1.8	1.9	V
AVDD3V	Analog buffer supply voltage		3.15	3.3	3.45	V
DRVDD	Digital supply voltage		1.7	1.8	1.9	V
ANALOG INPUTS
V_ID	Differential input voltage range	Default after reset		2		V_PP
V_ID	Differential input voltage range	Register programmable⁽¹⁾		2.5		V_PP
V_ICR	Input common-mode voltage		VCM ± 0.025			V
	Maximum analog input frequency with 2.5-V_PP input amplitude			250		MHz
	Maximum analog input frequency with 2-V_PP input amplitude			400		MHz
CLOCK INPUT
	Input clock sample rate	QDR interface	30		250	MSPS
	Input clock sample rate	DDR interface	10		250	MSPS
	Input clock amplitude differential (V_CLKP – V_CLKM)	Sine wave, ac-coupled	0.3⁽²⁾	1.5		V_PP
		LVPECL, ac-coupled		1.6
		LVDS, ac-coupled		0.7
		LVCMOS, single-ended, ac-coupled		1.5		V
	Input clock duty cycle		35%	50%	65%
DIGITAL OUTPUTS
C_LOAD	Maximum external load capacitance from each output pin to DRGND			3.3		pF
R_LOAD	Single-ended load resistance			+50		Ω
T_A	Operating free-air temperature		–40		+85	°C

(1) For details, refer to the Digital Gain section.

(2) Refer to the Performance vs Clock Amplitude curves, Figure 27 and Figure 28.

(3) After power-up, to reset the device for the first time, only use the RESET pin. Refer to the Register Initialization section.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		ADS42LBx9	UNIT
		RGC (VQFN)
		64 PINS
R_θJA	Junction-to-ambient thermal resistance	22.9	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	7.1	°C/W
R_θJB	Junction-to-board thermal resistance	2.5	°C/W
ψ_JT	Junction-to-top characterization parameter	0.1	°C/W
ψ_JB	Junction-to-board characterization parameter	2.5	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	0.2	°C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics: ADS42LB69 (16-Bit)

Typical values are at T_A = +25°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, 50% clock duty cycle, –1-dBFS differential analog input, and sampling rate = 250 MSPS, unless otherwise noted. Minimum and maximum values are across the full temperature range of T_MIN = –40°C to T_MAX = +85°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V.

PARAMETER		TEST CONDITIONS	2-V_PP FULL-SCALE			2.5-V_PP FULL-SCALE			UNIT
PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	MIN	TYP	MAX	UNIT
SNR	Signal-to-noise ratio	f_IN = 10 MHz		73.9			75.8		dBFS
		f_IN = 70 MHz		73.7			75.5
		f_IN = 170 MHz	70.8	73.2			74.7
		f_IN = 230 MHz		72.8			74.1
SINAD	Signal-to-noise and distortion ratio	f_IN = 10 MHz		73.7			75.1		dBFS
		f_IN = 70 MHz		73.6			75.3
		f_IN = 170 MHz	69.6	73.1			74.2
		f_IN = 230 MHz		72.5			73.4
SFDR	Spurious-free dynamic range (including second and third harmonic distortion)	f_IN = 10 MHz		87			83		dBc
		f_IN = 70 MHz		90			88
		f_IN = 170 MHz	81	87			85
		f_IN = 230 MHz		86			83
THD	Total harmonic distortion	f_IN = 10 MHz		86			82		dBc
		f_IN = 70 MHz		89			87
		f_IN = 170 MHz	78	85			82
		f_IN = 230 MHz		83			81
HD2	2nd-order harmonic distortion	f_IN = 10 MHz		97			95		dBc
		f_IN = 70 MHz		90			88
		f_IN = 170 MHz	81	87			85
		f_IN = 230 MHz		86			84
HD3	3rd-order harmonic distortion	f_IN = 10 MHz		87			83		dBc
		f_IN = 70 MHz		96			94
		f_IN = 170 MHz	81	91			85
		f_IN = 230 MHz		87			83
	Worst spur (other than second and third harmonics)	f_IN = 10 MHz		102			103		dBc
		f_IN = 70 MHz		101			103
		f_IN = 170 MHz	87	101			101
		f_IN = 230 MHz		100			100
IMD	Two-tone intermodulation distortion	f₁ = 46 MHz, f₂ = 50 MHz, each tone at –7 dBFS		97			94		dBFS
IMD	Two-tone intermodulation distortion	f₁ = 185 MHz, f₂ = 190 MHz, each tone at –7 dBFS		94			90		dBFS
	Crosstalk	20-MHz, full-scale signal on channel under observation; 170-MHz, full-scale signal on other channel		100			100		dB
	Input overload recovery	Recovery to within 1% (of full-scale) for 6-dB overload with sine-wave input		1			1		Clock cycle
PSRR	AC power-supply rejection ratio	For 50-mV_PP signal on AVDD supply, up to 10 MHz		> 40			> 40		dB
ENOB	Effective number of bits	f_IN = 170 MHz		11.85			12.03		LSBs
DNL	Differential nonlinearity	f_IN = 170 MHz		±0.6			±0.6		LSBs
INL	Integrated nonlinearity	f_IN = 170 MHz		±3	±8		±3.5		LSBs

6.6 Electrical Characteristics: ADS42LB49 (14-Bit)

PARAMETER		TEST CONDITIONS	2-V_PP FULL-SCALE			2.5-V_PP FULL-SCALE			UNIT
PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	MIN	TYP	MAX	UNIT
SNR	Signal-to-noise ratio	f_IN = 10 MHz		73.3			74.9		dBFS
		f_IN = 70 MHz		73.1			74.7
		f_IN = 170 MHz	69.5	72.7			74.1
		f_IN = 230 MHz		72.3			73.5
SINAD	Signal-to-noise and distortion ratio	f_IN = 10 MHz		73.1			74.1		dBFS
		f_IN = 70 MHz		73.1			74.4
		f_IN = 170 MHz	68.5	72.6			73.6
		f_IN = 230 MHz		72			72.9
SFDR	Spurious-free dynamic range (including second and third harmonic distortion)	f_IN = 10 MHz		87			82		dBc
		f_IN = 70 MHz		90			88
		f_IN = 170 MHz	79	87			85
		f_IN = 230 MHz		86			83
THD	Total harmonic distortion	f_IN = 10 MHz		86			81		dBc
		f_IN = 70 MHz		89			87
		f_IN = 170 MHz	76	85			82
		f_IN = 230 MHz		83			81
HD2	2nd-order harmonic distortion	f_IN = 10 MHz		97			95		dBc
		f_IN = 70 MHz		90			88
		f_IN = 170 MHz	79	87			85
		f_IN = 230 MHz		86			84
HD3	3rd-order harmonic distortion	f_IN = 10 MHz		87			82		dBc
		f_IN = 70 MHz		96			94
		f_IN = 170 MHz	79	91			85
		f_IN = 230 MHz		87			83
	Worst spur (other than second and third harmonics)	f_IN = 10 MHz		104			103		dBc
		f_IN = 70 MHz		101			103
		f_IN = 170 MHz	87	100			101
		f_IN = 230 MHz		99			100
IMD	Two-tone intermodulation distortion	f₁ = 46 MHz, f₂ = 50 MHz, each tone at –7 dBFS		99			95		dBFS
IMD	Two-tone intermodulation distortion	f₁ = 185 MHz, f₂ = 190 MHz, each tone at –7 dBFS		93			93		dBFS
	Crosstalk	20-MHz, full-scale signal on channel under observation; 170-MHz, full-scale signal on other channel		100			90		dB
	Input overload recovery	Recovery to within 1% (of full-scale) for 6-dB overload with sine-wave input		1			1		Clock cycle
PSRR	AC power-supply rejection ratio	For a 50-mV_PP signal on AVDD supply, up to 10 MHz		> 40			> 40		dB
ENOB	Effective number of bits	f_IN = 170 MHz		11.76			11.93		LSBs
DNL	Differential nonlinearity	f_IN = 170 MHz		±0.15			±0.15		LSBs
INL	Integrated nonlinearity	f_IN = 170 MHz		±0.75	±3		±0.9		LSBs

6.7 Electrical Characteristics: General

Typical values are at +25°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, 50% clock duty cycle, –1-dBFS differential analog input, and sampling rate = 250 MSPS, unless otherwise noted. Minimum and maximum values are across the full temperature range: T_MIN = –40°C to T_MAX = +85°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
ANALOG INPUTS
V_ID	Differential input voltage range	Default (after reset)		2		V_PP
V_ID	Differential input voltage range	Register programmed⁽¹⁾		2.5		V_PP
		Differential input resistance (at 170 MHz)		1.2		kΩ
		Differential input capacitance (at 170 MHz)		4		pF
	Analog input bandwidth	With 50-Ω source impedance, and 50-Ω termination		900		MHz
VCM	Common-mode output voltage			1.9		V
	VCM output current capability			10		mA
DC ACCURACY
	Offset error		–20		20	mV
E_GREF	Gain error as a result of internal reference inaccuracy alone			±2		%FS
E_GCHAN	Gain error of channel alone			–5		%FS
	Temperature coefficient of E_GCHAN			0.01		Δ%/°C
POWER SUPPLY
IAVDD	Analog supply current			141	182	mA
IAVDD3V	Analog buffer supply current			302	340	mA
IDRVDD	Digital and output buffer supply current	External 100-Ω differential termination on LVDS outputs		219	245	mA
	Analog power			253		mW
	Analog buffer power			996		mW
	Power consumption (includes digital blocks and output buffers)	External 100-Ω differential termination on LVDS outputs		393		mW
	Total power			1.64	1.85	W
	Global power-down (both channels)				160	mW

(1) Refer to the Serial Interface section.

6.8 Digital Characteristics

The dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level '0' or '1'. AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, and, unless otherwise noted.

PARAMETER			TEST CONDITIONS	MIN	TYP	MAX	UNIT
DIGITAL INPUTS (RESET, SCLK, SDATA, SEN, CTRL1, CTRL2)⁽¹⁾
V_IH	High-level input voltage		All digital inputs support 1.8-V and 3.3-V CMOS logic levels	1.3			V
V_IL	Low-level input voltage					0.4	V
I_IH	High-level input current	RESET, SDATA, SCLK, CTRL1, CTRL2⁽²⁾	V_HIGH = 1.8 V		10		µA
I_IH	High-level input current	SEN⁽³⁾	V_HIGH = 1.8 V		0		µA
I_IL	Low-level input current	RESET, SDATA, SCLK, CTRL1, CTRL2	V_LOW = 0 V		0		µA
I_IL	Low-level input current	SEN	V_LOW = 0 V		10		µA
DIGITAL OUTPUTS, CMOS INTERFACE (OVRA, OVRB, SDOUT)
V_OH	High-level output voltage			DRVDD – 0.1	DRVDD		V
V_OL	Low-level output voltage				0	0.1	V
DIGITAL OUTPUTS, LVDS INTERFACE
V_ODH	High-level output differential voltage		With an external 100-Ω termination	250	350	500	mV
V_ODL	Low-level output differential voltage		With an external 100-Ω termination	–500	–350	–250	mV
V_OCM	Output common-mode voltage				1.05		V

(1) SCLK, SDATA, and SEN function as digital input pins in serial configuration mode.

(2) SDATA and SCLK have an internal 150-kΩ pull-down resistor.

(3) SEN has an internal 150-kΩ pull-up resistor to AVDD. Because the pull-up resistor is weak, SEN can also be driven by 1.8-V or 3.3-V CMOS buffers.

6.9 Timing Requirements: General

Typical values are at +25°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, sampling frequency = 250 MSPS, sine wave input clock, C_LOAD = 3.3 pF, and R_LOAD = 100 Ω, unless otherwise noted. Minimum and maximum values are across the full temperature range: T_MIN = –40°C to T_MAX = +85°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.7 V to 1.9 V.

			MIN	TYP	MAX	UNIT
t_A	Aperture delay		0.5	0.7	1.1	ns
	Aperture delay matching between two channels of the same device			±70		ps
	Variation of aperture delay between two devices at the same temperature and supply voltage			±150		ps
t_J	Aperture jitter			85		f_S rms
	Wakeup time	Time to valid data after coming out of STANDBY mode		50	100	µs
	Wakeup time	Time to valid data after coming out of GLOBAL power-down mode (in this mode, both channels power-down)		250	1000	µs
	ADC latency⁽³⁾	Default latency after reset		14		Clock cycles
		Normal OVR latency		14		Clock cycles
		Fast OVR latency		9		Clock cycles
t_{SU_SYNCIN}	Setup time for SYNCIN, referenced to input clock rising edge		400			ps
t_{H_SYNCIN}	Hold time for SYNCIN, referenced to input clock rising edge		100			ps

6.10 Timing Requirements: DDR LVDS Mode⁽¹⁾

		MIN	TYP	MAX	UNIT
t_SU	Data setup time: data valid to zero-crossing of differential output clock (CLKOUTP – CLKOUTM)⁽²⁾	0.62	0.82		ns
t_HO	Data hold time: zero-crossing of differential output clock (CLKOUTP – CLKOUTM) to data becoming invalid⁽²⁾	0.54	0.64		ns
t_PDI	Clock propagation delay: input clock rising edge cross-over to output clock (CLKOUTP – CLKOUTM) rising edge cross-over	8	10.5	13	ns
	LVDS bit clock duty cycle: duty cycle of differential clock (CLKOUTP – CLKOUTM)		52%
t_FALL, t_RISE	Data fall time, data rise time: rise time measured from –100 mV to +100 mV, 10 MSPS ≤ sampling frequency ≤ 250 MSPS		0.14		ns
t_CLKRISE, t_CLKFALL	Output clock rise time, output clock fall time: Rise time measured from –100 mV to +100 mV, 10 MSPS ≤ sampling frequency ≤ 250 MSPS		0.18		ns

(1) Measurements are done with a transmission line of a 100-Ω characteristic impedance between the device and load. Setup and hold time specifications take into account the effect of jitter on the output data and clock.

(2) Data valid refers to a logic high of +100 mV and a logic low of –100 mV.

(3) Overall latency = ADC latency + t_PDI.

Table 1. DDR LVDS Timings at Lower Sampling Frequencies⁽¹⁾

SAMPLING FREQUENCY (MSPS)	SETUP TIME			HOLD TIME			CLOCK PROPAGATION DELAY			UNIT
	t_SU			t_HO			t_PDI
	MIN	TYP	MAX	MIN	TYP	MAX	MIN	TYP	MAX
80	2.40	2.96		2.16	2.82		9	11.9	15	ns
120	1.57	1.92		1.40	1.84		8	11.1	14
160	1.17	1.40		1.02	1.36		8	10.6	13
200	0.82	1.07		0.72	1.02		8	10.5	13
230	0.69	0.91		0.61	0.84		8	10.5	13

(1) See Figure 73 for a timing diagram in DDR LVDS mode.

6.11 Timing Requirements: QDR LVDS Mode⁽⁴⁾⁽¹⁾

Typical values are at +25°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, sampling frequency = 250 MSPS, sine-wave input clock, C_LOAD = 3.3 pF⁽²⁾, and R_LOAD = 100 Ω⁽³⁾, unless otherwise noted. Minimum and maximum values are across the full temperature range of T_MIN = –40°C to T_MAX = +85°C, AVDD = 1.8 V, AVDD3V = 3.3 V, and DRVDD = 1.7 V to 1.9 V.

		MIN	TYP	MAX	UNIT
t_SU	Data setup time⁽⁵⁾⁽⁶⁾: data valid to DxCLKP, DxCLKM zero-crossing	0.23	0.31		ns
t_H	Data hold time⁽⁵⁾⁽⁶⁾: DxCLKP, DxCLKM zero-crossing to data becoming invalid	0.16	0.29		ns
	LVDS bit clock duty cycle: differential bit clock duty cycle (DxCLKP, DxCLKM)		50%
t_PDI	Clock propagation delay: input clock rising edge cross-over to output frame clock (DxFRAMEP-DxFRAMEM) rising edge cross-over	7	10.1	13	ns
t_RISE, t_FALL	Data rise and fall time: rise time measured from –100 mV to +100 mV		0.18		ns
t_CLKRISE, t_CLKFALL	Output clock rise and fall time: rise time measured from –100 mV to +100 mV		0.2		ns

(1) Timing parameters are ensured by design and characterization and are not tested in production.

(2) C_LOAD is the effective external single-ended load capacitance between each output pin and ground.

(3) R_LOAD is the differential load resistance between the LVDS output pair.

(4) Measurements are done with a transmission line of 100-Ω characteristic impedance between the device and load. Setup and hold time specifications take into account the effect of jitter on the output data and clock.

(5) Data valid refers to a logic high of +100 mV and a logic low of –100 mV.

(6) The setup and hold times of a channel are measured with respect to the same channel output clock.

Table 2. QDR LVDS Timings at Lower Sampling Frequencies⁽¹⁾

SAMPLING FREQUENCY (MSPS)	SETUP TIME			HOLD TIME			CLOCK PROPAGATION DELAY			UNIT
	t_SU			t_HO			t_PDI
	MIN	TYP	MAX	MIN	TYP	MAX	MIN	TYP	MAX
80	1.06	1.21		0.84	1.29		6	9.3	12	ns
120	0.63	0.77		0.66	0.88		7	9.5	13
160	0.43	0.55		0.39	0.61		7	9.7	13
200	0.31	0.42		0.28	0.47		7	9.8	13
230	0.24	0.34		0.17	0.36		7	9.9	13

(1) See Figure 74 for a timing diagram in QDR LVDS mode.

6.12 Typical Characteristics: ADS42LB69

Typical values are at T_A = +25°C, full temperature range is T_MIN = –40°C to T_MAX = +85°C, ADC sampling rate = 250 MSPS, 50% clock duty cycle, QDR interface, AVDD3V = 3.3 V, AVDD = DRVDD = 1.8 V, –1-dBFS differential input, and 32k-point FFT, unless otherwise noted.

Figure 1. FFT for 10-MHz Input Signal

Figure 3. FFT for 300-MHz Input Signal

Figure 5. FFT for 170-MHz Input Signal
(2.5-V_PP Full-Scale)

Figure 7. FFT for Two-Tone Input Signal
(At –7 dBFS, 46 MHz and 50 MHz)

Figure 9. FFT for Two-Tone Input Signal
(At –7 dBFS, 185 MHz and 190 MHz)

Figure 11. IMD3 vs Input Amplitude
(46 MHz and 50 MHz)

Figure 13. SFDR vs Input Frequency

Figure 15. SFDR vs Digital Gain

Figure 17. Performance Across Input Amplitude
(70 MHz)

Figure 19. Performance vs Input Common-Mode Voltage
(70 MHz)

Figure 21. SFDR vs AVDD Supply and Temperature
(170 MHz)

Figure 23. SFDR vs AVDD_BUF Supply and Temperature (170 MHz)

Figure 25. SFDR vs DRVDD Supply and Temperature
(170 MHz)

Figure 27. Performance vs Clock Amplitude
(70 MHz)

Figure 29. Performance vs Clock Duty Cycle
(70 MHz)

Figure 2. FFT for 170-MHz Input Signal

Figure 4. FFT for 10-MHz Input Signal
(2.5-V_PP Full-Scale)

Figure 6. FFT for 300-MHz Input Signal
(2.5-V_PP Full-Scale)

Figure 8. FFT for Two-Tone Input Signal
(At –36 dBFS, 46 MHz and 50 MHz)

Figure 10. FFT for Two-Tone Input Signal
(At –36 dBFS, 185 MHz and 190 MHz)

Figure 12. IMD3 vs Input Amplitude
(185 MHz and 190 MHz)

Figure 14. SNR vs Input Frequency

Figure 16. SNR vs Digital Gain

Figure 18. Performance Across Input Amplitude
(170 MHz)

Figure 20. Performance vs Input Common-Mode Voltage (170 MHz)

Figure 22. SNR vs AVDD Supply and Temperature
(170 MHz)

Figure 24. SNR vs AVDD_BUF Supply and Temperature
(170 MHz)

Figure 26. SNR vs DRVDD Supply and Temperature
(170 MHz)

Figure 28. Performance vs Clock Amplitude
(170 MHz)

Figure 30. Performance vs Clock Duty Cycle
(170 MHz)

6.13 Typical Characteristics: ADS42LB49

Typical values are at T_A = +25°C, full temperature range is T_MIN = –40°C to T_MAX = +85°C, ADC sampling rate = 250 MSPS, 50% clock duty cycle, AVDD3V = 3.3 V, AVDD = DRVDD = 1.8 V, –1-dBFS differential input, and 32k-point FFT, unless otherwise noted.

Figure 31. FFT for 10-MHz Input Signal

Figure 33. FFT for 300-MHz Input Signal

Figure 35. FFT for 170-MHz Input Signal
(2.5-V_PP Full-Scale)

Figure 37. FFT for Two-Tone Input Signal
(At –7 dBFS, 46 MHz and 50 MHz)

Figure 39. FFT for Two-Tone Input Signal
(At –7 dBFS, 185 MHz and 190 MHz)

Figure 41. IMD3 vs Input Amplitude
(46 MHz and 50 MHz)

Figure 43. SFDR vs Input Frequency

Figure 45. SFDR vs Digital Gain

Figure 47. Performance Across Input Amplitude
(70 MHz)

Figure 49. Performance vs Input Common-Mode Voltage
(70 MHz)

Figure 51. SFDR vs AVDD Supply and Temperature
(170 MHz)

Figure 53. SFDR vs AVDD_BUF Supply and Temperature (170 MHz)

Figure 55. SFDR vs DRVDD Supply and Temperature
(170 MHz)

Figure 57. Performance vs Clock Amplitude
(70 MHz)

Figure 59. Performance vs Clock Duty Cycle
(70 MHz)

Figure 32. FFT for 170-MHz Input Signal

Figure 34. FFT for 10-MHz Input Signal
(2.5-V_PP Full-Scale)

Figure 36. FFT for 300-MHz Input Signal
(2.5-V_PP Full-Scale)

Figure 38. FFT for Two-Tone Input Signal
(At –36 dBFS, 46 MHz and 50 MHz)

Figure 40. FFT for Two-Tone Input Signal
(At –36 dBFS, 185 MHz and 190 MHz)

Figure 42. IMD3 vs Input Amplitude
(185 MHz and 190 MHz)

Figure 44. SNR vs Input Frequency

Figure 46. SNR vs Digital Gain

Figure 48. Performance Across Input Amplitude
(170 MHz)

Figure 50. Performance vs Input Common-Mode Voltage (170 MHz)

Figure 52. SNR vs AVDD Supply and Temperature
(170 MHz)

Figure 54. SNR vs AVDD_BUF Supply and Temperature
(170 MHz)

Figure 56. SNR vs DRVDD Supply and Temperature
(170 MHz)

Figure 58. Performance vs Clock Amplitude
(170 MHz)

Figure 60. Performance vs Clock Duty Cycle
(170 MHz)

6.14 Typical Characteristics: Common

Figure 61. CMRR FFT

Figure 63. PSRR FFT for AVDD Supply

Figure 65. Total Power vs Sampling Frequency

Figure 62. CMRR vs Test Signal Frequency

Figure 64. PSRR vs Test Signal Frequency

6.15 Typical Characteristics: Contour

6.15.1 Spurious-Free Dynamic Range (SFDR): General

Figure 66. SFDR (0-dB Gain)

Figure 67. SFDR (6-dB Gain)

6.15.2 Signal-to-Noise Ratio (SNR): ADS42LB69

Figure 68. SNR (0-dB Gain, 16 Bits)

Figure 69. SNR (6-dB Gain, 16 Bits)

6.15.3 Signal-to-Noise Ratio (SNR): ADS42LB49

Figure 70. SNR (0-dB Gain, 14 Bits)

Figure 71. SNR (6-dB Gain, 14 Bits)

7 Parameter Measurement Information

ADS42LB49 ADS42LB69 tim_syncin_las904.gif

Figure 72. Timing Diagram for SYNCINP and SYNCINM Inputs

ADS42LB49 ADS42LB69 tim_DDR_LVDS_out_las904.gif

Figure 73. DDR LVDS Output Timing Diagram

ADS42LB49 ADS42LB69 tim_DDR2X_LVDS_out_las904.gif

Figure 74. QDR LVDS Output Timing Diagram

ADS42LB49 ADS42LB69 tim_lvds_vo_level_bas550.gif

NOINDENT:

With an external 100-Ω termination.

Figure 75. DDR LVDS Output Voltage Levels