The bq24298 is a highly-integrated switch-mode battery charge management and system power path management device for 1 cell Li-Ion and Li-polymer battery in a wide range of smart phone and tablet applications. Its low impedance power path optimizes switch-mode operation efficiency, reduces battery charging time and extends battery life during discharging phase.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
bq24298 | WQFN (24) | 4.00 mm x 4.00 mm |
Changes from * Revision (April 2015) to A Revision
The I2C serial interface with charging and system settings makes the device a truly flexible solution.
The device supports 3.9V – 6.2V USB input sources, including standard USB host port and USB charging port with 6.4V over-voltage protection. The device supports USB 2.0 and USB 3.0 power specifications with input current and voltage regulation. To set the default input current limit, the bq24298 takes the result from the detection circuit in the system, such as USB PHY device. The device also supports USB On-the-Go operation by providing fast startup and supplying adjustable voltage 4.55 – 5.5V (default 5V) on the VBUS with an accurate current limit up to 1.5A.
The power path management regulates the system slightly above battery voltage but does not drop below 3.5V minimum system voltage (programmable). With this feature, the system keeps operating even when the battery is completely depleted or removed. When the input source current or voltage limit is reached, the power path management automatically reduces the charge current to zero and then starts discharges the battery until the system power requirement is met. This supplement mode operation keeps the input source from getting overloaded.
The device initiates and completes a charging cycle when host control is not available. It automatically charges the battery in three phases: pre-conditioning, constant current and constant voltage. In the end, the charger automatically terminates when the charge current is below a preset limit in the constant voltage phase. Later on, when the battery voltage falls below the recharge threshold, the charger will automatically start another charging cycle.
The charge device provides various safety features for battery charging and system operation, including negative thermistor monitoring, charging safety timer and over-voltage/over-current protections. The thermal regulation reduces charge current when the junction temperature exceeds 120°C (programmable).
The STAT output reports the charging status and any fault conditions. The INT immediately notifies host when fault occurs.
The bq24298 is available in a 24-pin, 4.00-mm x 4.00-mm thin WQFN package.
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NAME | NUMBER | ||
VBUS | 1,24 | P | Charger Input Voltage. The internal n-channel reverse block MOSFET (RBFET) is connected between VBUS and PMID with VBUS on source. Place a 1-µF ceramic capacitor from VBUS to PGND and place it as close as possible to IC. |
PSEL | 2 | I | Power source selection input. High indicates a USB host source and Low indicates an adapter source. |
PG | 3 | O | Open drain active low power good indicator. Connect to the pull up rail via 10-kΩ resistor. LOW indicates a good input source if the input voltage is between UVLO and ACOV, above SLEEP mode threshold, and current limit is above 30 mA. |
STAT | 4 | O | Open drain charge status output to indicate various charger operation. Connect to the pull up rail via 10-kΩ resistor. LOW indicates charge in progress. HIGH indicates charge complete or charge disabled. When any fault condition occurs, STAT pin in the charge blinks at 1 Hz. |
SCL | 5 | I | I2C Interface clock. Connect SCL to the logic rail through a 10-kΩ resistor. |
SDA | 6 | I/O | I2C Interface data. Connect SDA to the logic rail through a 10-kΩ resistor. |
INT | 7 | O | Open-drain Interrupt Output. Connect the INT to a logic rail via 10kΩ resistor. The INT pin sends active low, 256-µs pulse to host to report charger device status and fault. |
OTG | 8 | I Digital |
USB current limit selection pin during buck mode, and active high enable pin during boost mode. |
For bq24298, when in buck mode with USB host (PSEL = High), when OTG = High, IIN limit = 500 mA and when OTG = Low, IIN limit = 100 mA. | |||
The boost mode is activated when the REG01[5] = 1 and OTG pin is High. | |||
CE | 9 | I | Active low Charge Enable pin. Battery charging is enabled when REG01[5:4] = 01 and CE pin = Low. CE pin must be pulled high or low. |
ILIM | 10 | I | ILIM pin sets the maximum input current limit by regulating the ILIM voltage at 1 V. A resistor is connected from ILIM pin to ground to set the maximum limit as IINMAX = (1V/RILIM) × KILIM. The actual input current limit is the lower one set by ILIM and by I2C REG00[2:0]. The minimum input current programmed on ILIM pin is 500 mA. |
TS | 11 | I Analog |
Temperature qualification voltage input. Connect a negative temperature coefficient thermistor. Program temperature window with a resistor divider from REGN to TS to GND. Charge suspends or Boost disable when TS pin is out of range. A 103AT-2 thermistor is recommended. |
QON | 12 | I | BATFET enables control in shipping mode and BATFET reset function. Logic high to low transition on this pin with at least tQON_ON_1 deglitch turns on BATFET to exit shipping mode. It has internal pull up to maintain default high logic. When VBUS is not plugged-in, a logic low of at least tQON_RST will reset SYS power by turning BATFET off for tBATFET_RST and then re-enable BATFET after tBATFET_RST duration. The pin integrates a pull-up resistor of typical 187 kΩ. |
BAT | 13,14 | P | Battery connection point to the positive pin of the battery pack. The internal BATFET is connected between BAT and SYS. Connect a 10 µF closely to the BAT pin. |
SYS | 15,16 | I | System connection point. The internal BATFET is connected between BAT and SYS. When the battery falls below the minimum system voltage, switch-mode converter keeps SYS above the minimum system voltage. The SYS pin has a built-in load to ground which may discharge 330-µF load to less than 0.3 V within 250 ms typically. |
PGND | 17,18 | P | Power ground connection for high-current power converter node. Internally, PGND is connected to the source of the n-channel LSFET. On PCB layout, connect directly to ground connection of input and output capacitors of the charger. A single point connection is recommended between power PGND and the analog GND near the IC PGND pin. |
SW | 19,20 | O | Switching node connecting to output inductor. Internally SW is connected to the source of the n-channel HSFET and the drain of the n-channel LSFET. Connect the 0.047-µF bootstrap capacitor from SW to BTST. |
BTST | 21 | P | PWM high side driver positive supply. Internally, the BTST is connected to the anode of the boost-strap diode. Connect the 0.047-µF bootstrap capacitor from SW to BTST. |
REGN | 22 | P | PWM low side driver positive supply output. Internally, REGN is connected to the cathode of the boost-strap diode. Connect a 4.7-µF (10-V rating) ceramic capacitor from REGN to analog GND. The capacitor should be placed close to the IC. REGN also serves as bias rail of TS pin. |
Thermal Pad | P | Exposed pad beneath the IC for heat dissipation. Always solder thermal pad to the board, and have vias on the thermal pad plane star-connecting to PGND and ground plane for high-current power converter. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Voltage (with respect to GND) |
VBUS (converter not switching) | –2 | 15(2) | V |
PMID (converter not switching) | –0.3 | 15(2) | V | |
STAT, PG | –0.3 | 12 | V | |
BTST | –0.3 | 12 | V | |
SW | –2 | 7 8 (Peak for 20ns duration) |
V | |
BAT, SYS (converter not switching) | –0.3 | 6 | V | |
SDA, SCL, INT, OTG, ILIM, REGN, TS, QON, CE PSEL | –0.3 | 7 | V | |
BTST TO SW | –0.3 | 7 | V | |
PGND to GND | –0.3 | 0.3 | V | |
Output sink current | INT, STAT, PG | 6 | mA | |
Junction temperature | –40 | 150 | °C | |
Storage temperature range, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | 1000 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101(2) | 250 | V |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VIN | Input voltage | 3.9 | 6.2(1) | V |
ISYS | Output current (SYS) | 3.5 | A | |
VBAT | Battery voltage | 4.4 | V | |
IBAT | Fast charging current | 3 | A | |
Discharging current with internal MOSFET | 5.5 | A | ||
TA | Operating free-air temperature range | –40 | 85 | °C |
THERMAL METRIC(1) | bq24298 | UNIT | |
---|---|---|---|
RTW (WQFN) | |||
24 PIN | |||
RθJA | Junction-to-ambient thermal resistance | 32.2 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 29.8 | °C/W |
RθJB | Junction-to-board thermal resistance | 9.1 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.3 | °C/W |
ψJB | Junction-to-board characterization parameter | 9.1 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 2.2 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
QUIESCENT CURRENTS | ||||||
IBAT | Battery discharge current (BAT, SW, SYS) | VVBUS < VUVLO, VBAT = 4.2 V, leakage between BAT and VBUS, TJ < 85°C | 5 | µA | ||
High-Z Mode, or no VBUS, BATFET disabled (REG07[5] = 1), –40°C – 85°C | 16 | 20 | µA | |||
High-Z Mode, or no VBUS, BATFET enabled (REG07[5] = 0), –40°C – 85°C | 32 | 55 | µA | |||
IVBUS | Input supply current (VBUS) | VVBUS = 5 V, High-Z mode, No battery | 15 | 30 | µA | |
VVBUS > VUVLO, VVBUS > VBAT, converter not switching | 1.5 | 3 | mA | |||
VVBUS > VUVLO, VVBUS > VBAT, converter switching, VBAT = 3.2 V, ISYS = 0 A | 4 | mA | ||||
VVBUS > VUVLO, VVBUS > VBAT, converter switching, charge disable, VBAT = 3.8 V, ISYS = 100 µA | 3.5 | mA | ||||
IBOOST | Battery discharge current in boost mode | VBAT = 4.2 V, Boost mode, IVBUS = 0 A, converter switching | 3.5 | mA | ||
VBUS/BAT POWER UP | ||||||
VVBUS_OP | VBUS operating voltage | 3.9 | 6.2 | V | ||
VVBUS_UVLOZ | VBUS for active I2C, no battery | VVBUS rising | 3.6 | V | ||
VSLEEP | Sleep mode falling threshold | VVBUS falling, VVBUS-VBAT | 35 | 80 | 120 | mV |
VSLEEPZ | Sleep mode rising threshold | VVBUS rising, VVBUS-VBAT | 170 | 250 | 350 | mV |
VACOV | VBUS over-voltage rising threshold | VVBUS rising | 6.2 | 6.6 | V | |
VACOV_HYST | VBUS over-voltage falling hysteresis | VVBUS falling | 250 | mV | ||
VBAT_UVLOZ | Battery for active I2C, no VBUS | VBAT rising | 2.3 | V | ||
VBAT_DPL | Battery depletion threshold | VBAT falling | 2.4 | 2.6 | V | |
VBAT_DPL_HY | Battery depletion rising hysteresis | VBAT rising | 200 | mV | ||
VVBUSMIN | Bad adapter detection threshold | VVBUS falling | 3.8 | V | ||
IBADSRC | Bad adapter detection current source | 30 | mA | |||
POWER PATH MANAGEMENT | ||||||
VSYS_MAX | Maximum DC system voltage output | BATFET (Q4) off, VBAT up to 4.35 V
|
4.43 | V | ||
VSYS_MIN | Minimum DC system voltage output | REG01[3:1] = 101, VSYSMIN = 3.5 V | 3.5 | 3.65 | V | |
RON(RBFET) | Top reverse blocking MOSFET on-resistance between VBUS and PMIID | 28 | 41 | mΩ | ||
RON(HSFET) | Internal top switching MOSFET on-resistance between PMID and SW | TJ = –40°C – 85°C | 39 | 51 | mΩ | |
TJ = -40°C – 125°C | 39 | 58 | ||||
RON(LSFET) | Internal bottom switching MOSFET on-resistance between SW and PGND | TJ = –40°C – 85°C | 61 | 82 | mΩ | |
TJ = -40°C – 125°C | 61 | 90 | ||||
VFWD | BATFET forward voltage in supplement mode | BAT discharge current 10mA | 30 | mV | ||
VSYS_BAT | SYS/BAT comparator | VBAT < VSYSMIN , VSYS falling | 80 | mV | ||
VBAT > VSYSMIN , VSYS falling | 180 | mV | ||||
VBATGD | Battery good comparator rising threshold | VBAT rising | 3.55 | V | ||
VBATGD_HYST | Battery good comparator falling threshold | VBAT falling | 100 | mV | ||
BATTERY CHARGER | ||||||
VBAT_REG_ACC | Charge voltage regulation accuracy | VBAT = 4.112 V and 4.208 V | –0.5% | 0.5% | ||
IICHG_REG_ACC | Fast charge current regulation accuracy | VBAT = 3.8 V, ICHG = 1024 mA, TJ = 25°C | -4% | 4% | ||
VBAT = 3.8 V, ICHG = 1024 mA, TJ = -20°C – 125°C | -7% | 7% | ||||
VBAT = 3.8 V, ICHG = 1792 mA, TJ = -20°C – 125°C | –10% | 10% | ||||
ICHG_20pct | Charge current with 20% option on | VBAT = 3.1 V, ICHG = 104 mA, REG02 = 03 and REG02[0] = 1 | 75 | 175 | mA | |
VBATLOWV | Battery LOWV falling threshold | Fast charge to precharge, REG04[1] = 1 | 2.6 | 2.8 | 2.9 | V |
VBATLOWV_HYST | Battery LOWV rising threshold | Precharge to fast charge, REG04[1] = 1 (Typical 200-mV hysteresis) |
2.8 | 3.0 | 3.1 | V |
IPRECHG_ACC | Precharge current regulation accuracy | VBAT = 2.6 V, ICHG = 256 mA | –20% | 20% | ||
ITYP_TERM_ACC | Typical termination current | ITERM = 256 mA, ICHG = 2048 mA | 256 | mA | ||
ITERM_ACC | Termination current accuracy | ITERM = 256 mA, ICHG = 2048 mA | –20% | 20% | ||
VSHORT | Battery short voltage | VBAT falling | 2.0 | V | ||
VSHORT_HYST | Battery Short Voltage hysteresis | VBAT rising | 200 | mV | ||
ISHORT | Battery short current | VBAT < 2.2 V | 100 | mA | ||
VRECHG | Recharge threshold below VBAT_REG | VBAT falling, REG04[0] = 0 | 100 | mV | ||
tRECHG | Recharge deglitch time | VBAT falling, REG04[0] = 0 | 20 | ms | ||
RON_BATFET | SYS-BAT MOSFET on-resistance | TJ = 25°C | 24 | 28 | mΩ | |
TJ = –20°C – 125°C | 24 | 35 | ||||
INPUT VOLTAGE/CURRENT REGULATION | ||||||
VINDPM_REG_ACC | Input voltage regulation accuracy | -2% | 2% | |||
IUSB_DPM | USB Input current regulation limit, VBUS = 5V, current pulled from SW | USB100 | 85 | 100 | mA | |
USB150 | 125 | 150 | mA | |||
USB500 | 440 | 500 | mA | |||
USB900 | 750 | 900 | mA | |||
IADPT_DPM | Input current regulation accuracy | IADP = 1.5 A, REG00[2:0] = 101 | 1.3 | 1.5 | A | |
IIN_START | Input current limit during system start up | VSYS < 2.2 V | 100 | mA | ||
KILIM | IIN = KILIM/RILIM | 395 | 435 | 475 | A x Ω | |
BAT OVER-VOLTAGE PROTECTION | ||||||
VBATOVP | Battery over-voltage threshold | VBAT rising, as percentage of VBAT_REG | 104% | |||
VBATOVP_HYST | Battery over-voltage hysteresis | VBAT falling, as percentage of VBAT_REG | 2% | |||
tBATOVP | Battery over-voltage deglitch time to disable charge | 1 | µs | |||
THERMAL REGULATION AND THERMAL SHUTDOWN | ||||||
TJunction_REG | Junction temperature regulation accuracy | REG06[1:0] = 11 | 120 | °C | ||
TSHUT | Thermal shutdown rising temperature | Temperature increasing | 160 | °C | ||
TSHUT_HYS | Thermal shutdown hysteresis | 30 | °C | |||
Thermal shutdown rising deglitch | Temperature increasing delay | 1 | ms | |||
Thermal shutdown falling deglitch | Temperature decreasing delay | 1 | ms | |||
COLD/HOT THERMISTER COMPARATOR | ||||||
VLTF | Cold temperature threshold, TS pin voltage rising threshold | Charger suspends charge. as percentage to VREGN | 73% | 73.5% | 74% | |
VLTF_HYS | Cold temperature hysteresis, TS pin voltage falling | As percentage to VREGN | 0.4% | |||
VHTF | Hot temperature TS pin voltage rising threshold | As percentage to VREGN | 46.6% | 47.2% | 48.8% | |
VTCO | Cut-off temperature TS pin voltage falling threshold | As percentage to VREGN | 44.2% | 44.7% | 45.2% | |
Deglitch time for temperature out of range detection | VTS > VLTF, or VTS < VTCO, or VTS < VHTF | 10 | ms | |||
VBCOLD0 | Cold temperature threshold, TS pin voltage rising threshold | As percentage to VREGN REG02[1] = 0 (Approx. -10°C w/ 103AT) |
75.5% | 76% | 76.5% | |
VBCOLD0_HYS | As percentage to VREGN REG02[1] = 0 (Approx. 1°C w/ 103AT) |
1% | ||||
VBCOLD1 | Cold temperature threshold 1, TS pin voltage rising threshold | As percentage to VREGN REG02[1] = 1 (Approx. -20°C w/ 103AT) |
78.5% | 79% | 79.5% | |
VBCOLD1_HYS | As percentage to VREGN REG02[1] = 1 (Approx. 1°C w/ 103AT) |
1% | ||||
VBHOT0 | Hot temperature threshold, TS pin voltage falling threshold | As percentage to VREGN REG06[3:2] = 01 (Approx. 55°C w/ 103AT) |
35.5% | 36% | 36.5% | |
VBHOT0_HYS | As percentage to VREGN REG06[3:2] = 01 (Approx. 3°C w/ 103AT) |
3% | ||||
VBHOT1 | Hot temperature threshold 1, TS pin voltage falling threshold | As percentage to VREGN REG06[3:2] = 00 (Approx. 60°C w/ 103AT) |
32.5% | 33% | 33.5% | |
VBHOT1_HYS | As percentage to VREGN REG06[3:2] = 00 (Approx. 3°C w/ 103AT) |
3% | ||||
VBHOT2 | Hot temperature threshold 2, TS pin voltage falling threshold | As percentage to VREGN REG06[3:2] = 10 (Approx. 65°C w/ 103AT) |
29.5% | 30% | 30.5% | |
VBHOT2_HYS | As percentage to VREGN REG06[3:2] = 10 (Approx. 3°C w/ 103AT) |
3% | ||||
CHARGE OVER-CURRENT COMPARATOR | ||||||
IHSFET_OCP | HSFET cycle by cycle over-current threshold | 5.3 | 7.5 | A | ||
VLSFET_UCP | LSFET charge under-current falling threshold | From sync mode to non-sync mode | 100 | mA | ||
FSW | PWM Switching frequency, and digital clock | 1300 | 1500 | 1700 | kHz | |
DMAX | Maximum PWM duty cycle | 97% | ||||
VBTST_REFRESH | Bootstrap refresh comparator threshold | VBTST-VSW when LSFET refresh pulse is requested, VBUS = 5 V | 3.6 | V | ||
BOOST MODE OPERATION | ||||||
VOTG_REG_ACC | OTG output voltage | I(VBUS) = 0, REG06[7:4] = 0111 (4.998 V) | 5 | V | ||
VOTG_REG_ACC | OTG output voltage accuracy | I(VBUS) = 0, REG06[7:4] = 0111 (4.998 V) | -3% | 3% | ||
VOTG_BAT | Battery voltage exiting OTG mode | BAT falling, REG04[1] = 1 | 2.9 | V | ||
IOTG | OTG mode output current | REG01[0] = 0 | 1 | A | ||
REG01[0] = 1 | 1.5 | A | ||||
VOTG_OVP | OTG over-voltage threshold | Rising threshold | 5.8 | 6 | V | |
VOTG_OVP_HYS | OTG over-voltage threshold hysteresis | Falling threshold | 300 | mV | ||
IOTG_LSOCP | LSFET cycle by cycle current limit | 5 | A | |||
IOTG_HSZCP | HSFET under current falling threshold | 100 | mA | |||
IRBFET_OCP | RBFET over-current threshold | REG01[0] = 0 | 1.00 | 1.15 | 1.30 | A |
REG01[0] = 1 | 1.50 | 1.70 | 1.90 | |||
REGN LDO | ||||||
VREGN | REGN LDO output voltage | VVBUS = 6 V, IREGN = 40 mA | 4.8 | 5 | 5.5 | V |
VVBUS = 5 V, IREGN = 20 mA | 4.7 | 4.8 | V | |||
IREGN | REGN LDO current limit | VVBUS = 5 V, VREGN = 3.8 V | 50 | mA | ||
LOGIC I/O PIN CHARACTERISTICS (OTG, CE, STAT, QON, PSEL, PG) | ||||||
VILO | Input low threshold | 0.4 | V | |||
VIH | Input high threshold (CE, STAT, QON, PSEL, PG) | 1.3 | V | |||
VIH_OTG | Input high threshold (OTG) | 1.1 | V | |||
VOUT_LO | Output low saturation voltage | Sink current = 5 mA | 0.4 | V | ||
IBIAS | High level leakage current (OTG, CE, STAT , PSEL, PG) | Pull-up rail 1.8 V | 1 | µA | ||
IBIAS | High level leakage current (QON) | Pull-up rail 3.6 V | 8 | µA | ||
I2C INTERFACE (SDA, SCL, INT) | ||||||
VIH | Input high threshold level | VPULL-UP = 1.8 V, SDA and SCL | 1.3 | V | ||
VIL | Input low threshold level | VPULL-UP = 1.8 V, SDA and SCL | 0.4 | V | ||
VOL | Output low threshold level | Sink current = 5 mA | 0.4 | V | ||
IBIAS | High-level leakage current | VPULL-UP = 1.8 V, SDA and SCL | 1 | µA | ||
fSCL | SCL clock frequency | 400 | kHz | |||
DIGITAL CLOCK AND WATCHDOG TIMER | ||||||
fHIZ | Digital crude clock | REGN LDO disabled | 15 | 35 | 50 | kHz |
fDIG | Digital clock | REGN LDO enabled | 1300 | 1500 | 1700 | kHz |
MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|
VBUS/BAT POWER UP | ||||||
tBADSRC | Bad source detection duration | 30 | ms | |||
BOOST MODE OPERATION | ||||||
tOTG_OCP_OFF | OTG mode over-current protection off cycle time | 32 | ms | |||
tOTG_OCP_ON | OTG mode over-current protection on cycle time | 450 | µs | |||
QON TIMING | ||||||
tQON_ON_1 | QON low time to turn on BATFET and exit ship mode | 0.6 | 1.5 | s | ||
tQON_RST | QON low time to reset BATFET | 10 | 12.5 | 15 | s | |
tBATFET_RST | BATFET reset duration | 250 | 400 | ms | ||
LOGIC I/O PIN CHARACTERISTICS (OTG, CE, STAT, QON, PSEL, PG) | ||||||
tBATFET_DLY | BATFET disable delay time | 7 | 9 | 11 | s | |
DIGITAL CLOCK AND WATCHDOG TIMER | ||||||
tWDT | REG05[5:4] = 11 | REGN LDO disabled | 138 | 172 | s | |
REGN LDO enabled | 138 | 168 |
FIGURE | |
---|---|
Charging Efficiency vs Charging Current (DCR = 10 mΩ) | Figure 2 |
System Efficiency vs System Load Current (DCR = 10 mΩ) | Figure 3 |
Boost Mode Efficiency vs VBUS Load Current (DCR = 10 mΩ) | Figure 4 |
SYS Voltage Regulation vs System Load Current | Figure 5 |
Boost Mode VBUS Voltage Regulation (Typical Output = 4.998 V, REG06[7:4] = 0111) vs VBUS Load Current | Figure 6 |
SYS Voltage vs Temperature | Figure 7 |
BAT Voltage vs Temperature | Figure 8 |
Input Current Limit vs Temperature | Figure 9 |
Charge Current vs Package Temperature | Figure 10 |
Typical Output = 4.998 V, REG06[7:4] = 0111 | ||