DATA SHEET
CDCLVP111-SP 低電圧、1:10 LVPECL、クロック・ドライバ、入力切り換え付き
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1 特長
- 1つの差動クロック入力ペアLVPECLを10の差動LVPECLへ分配
- LVECLおよびLVPECLと完全に互換
- 2.375V～3.8Vの広い電源電圧範囲に対応
- CLK_SELによりクロック入力を選択可能
- クロック分配アプリケーションでの低い出力スキュー(標準値15ps)
- 付加ジッタ: 1ps未満
- 伝搬遅延: 355ps未満
- オープン入力デフォルト状態
- LVDS、CML、SSTL入力互換
- シングルエンド・クロック用のVBB基準電圧出力
- 周波数範囲: DC～3.5GHz
-
防衛、航空宇宙、および医療アプリケーションをサポート
- 管理されたベースライン
- 単一のアセンブリ/テスト施設
- 単一の製造施設
- 軍用温度範囲(-55℃～125℃)で利用可能 (1)
- 長期にわたる製品ライフ・サイクル
- 製品変更通知の延長
- 製品のトレーサビリティ
1. 温度範囲をカスタマイズ可能
2 アプリケーション
- 50Ωの伝送経路を駆動するよう設計
- 高性能のクロック分配
- エンジニアリング評価(/EM)サンプルを利用可能 (1)
1. これらのユニットは、技術的な評価のみを目的としています。標準とは異なるフロー(バーンインがないなど)に従って処理されており、25℃の温度定格のみがテストされれています。これらのユニットは、認定、量産、放射線テスト、航空での使用には適していません。これらの部品は、MILに規定されている温度範囲-55℃～125℃での動作時間全体にわたるパフォーマンスを保証されていません。
3 概要
CDCLVP111-SPクロック・ドライバは、LVPECL入力の1つの差動クロックペア(CLK0、CLK1)を、10ペアの差動LVPECLクロック(Q0～Q9)出力に、最小限のスキューで分配します。CDCLVP111-SPは、入力マルチプレクサに2つのクロック源を接続できます。CDCLVP111-SPは、50Ωの伝送経路を駆動するように特化して設計されています。出力ピンが使用されていないときは、消費電力を削減するためオープンのままにしておくことをお勧めします。差動ペアの出力ピンのうち一方だけを使用する場合、他方の出力ピンは同様に50Ωに終端する必要があります。
シングルエンド入力動作が必要な場合は、VBB基準電圧出力を使用します。この場合、VBBピンをCLK0へ接続し、10nFのコンデンサを経由してGNDへバイパスします。
高速性能を発揮するには、差動モードの使用を強く推奨します。
CDCLVP111-SPは、-55℃～125℃での動作が規定されています。
製品情報(1)
| 型番 | パッケージ | 本体サイズ(公称) |
|---|---|---|
| CDCLVP111-SP | HFG (36) | 9.08mm×9.08mm |
- 利用可能なすべてのパッケージについては、このデータシートの末尾にある注文情報を参照してください。
機能ブロック図
4 改訂履歴
Changes from * Revision (November 2016) to A Revision
- Added エンジニアリング評価サンプルの箇条書きと脚注を、「アプリケーション」セクションにGo
5 Pin Configuration and Functions
HFG Package
36-Pin CFP
Top View
Pin Functions(1)
| PIN | TYPE | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| CLK_SEL | 2 | Input | Clock select. Used to select between CLK0 and CLK1 input pairs. LVTTL/LVCMOS functionality compatible. |
| CLK0, CLK0 | 3, 4 | Input | Differential LVECL/LVPECL input pair. |
| CLK1, CLK1 | 6, 7 | Input | |
| Q[9:0] | 12, 14, 16, 20, 22, 24, 26, 30, 32, 34 | Output | LVECL/LVPECL clock outputs, these outputs provide low-skew copies of CLKn. |
| Q[9:0] | 11, 13, 15, 19, 21, 23, 25, 29, 31, 33 | Output | LVECL/LVPECL complementary clock outputs, these outputs provide copies of CLKn. |
| VBB | 5 | Power | Reference voltage output for single-ended input operation. |
| VCC | 1, 9, 10, 17, 18, 27, 28, 35, 36 | Power | Supply voltage. |
| VEE | 8 | Power | Device ground or negative supply voltage in ECL mode. |
(1) CLKn, CLK_SEL pull down resistor = 75 kΩ; CLKn pull up resistor = 37.5 kΩ; CLKn pull down resistor = 50 kΩ.
6 Specifications
6.1 Absolute Maximum Ratings
see (1)| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| VCC | Supply voltage (relative to VEE) | –0.3 | 4.6 | V |
| VI | Input voltage | –0.3 | VCC + 0.5 | V |
| VO | Output voltage | –0.3 | VCC + 0.5 | V |
| IIN | Input current | ±20 | mA | |
| VEE | Negative supply voltage (relative to VCC) | –4.6 | 0.3 | V |
| IBB | Sink/source current | –1 | 1 | mA |
| IO | DC output current | –50 | mA | |
| TJ | Maximum operating junction temperature | 150 | °C | |
| Tstg | Storage temperature | –65 | 150 | °C |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
| Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 | |||
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
| MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|
| VCC | Supply voltage (relative to VEE) | 2.375 | 2.5/3.3 | 3.8 | V |
| TJ | Operating junction temperature | –55 | 125 | °C | |
6.4 Thermal Information
| THERMAL METRIC(1) | CDCLVP111-SP | UNIT | ||
|---|---|---|---|---|
| HFG (CFP) | ||||
| 36 PINS | ||||
| RθJA | Junction-to-ambient thermal resistance(2) | 107.2 | °C/W | |
| RθJC(top) | Junction-to-case (top) thermal resistance | 33.2 | °C/W | |
| RθJB | Junction-to-board thermal resistance | 98.9 | °C/W | |
| ψJT | Junction-to-top characterization parameter | 29.2 | °C/W | |
| ψJB | Junction-to-board characterization parameter | 91.36 | °C/W | |
| RθJC(bot) | Junction-to-case (bottom) thermal resistance | 13.4 | °C/W | |
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
(2) According to JESD 51-7 standard.
6.5 LVECL DC Electrical Characteristics
Vsupply: VCC = 0 V, VEE = –2.375 V to –3.8 V over operating temperature range TJ = –55°C to 125°C (unless otherwise noted)| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| IEE | Supply internal current | Absolute value of current | –55°C, 25°C, 125°C | 30 | 85 | mA | |
| ICC | Output and internal supply current | All outputs terminated 50 Ω to VCC – 2 V | –55°C, 25°C | 385 | mA | ||
| 125°C | 405 | ||||||
| IIN | Input current | Includes pullup and pulldown resistors, VIH = VCC, VIL = VCC – 2 V |
–55°C, 25°C, 125°C | –150 | 150 | μA | |
| VBB | Internally generated bias voltage | For VEE = –3 V to –3.8 V, IBB = –0.2 mA | –55°C, 25°C, 125°C | –1.45 | –1.3 | –1.125 | V |
| VEE = –2.375 V to –2.75 V, IBB = –0.2 mA | –55°C, 25°C, 125°C | –1.3 | –1.25 | –1.1 | |||
| VIH | High-level input voltage (CLK_SEL) | –55°C, 25°C, 125°C | –1.165 | –0.88 | V | ||
| VIL | Low-level input voltage (CLK_SEL) | –55°C, 25°C, 125°C | –1.81 | –1.475 | V | ||
| VID | Input amplitude (CLKn, CLKn) | Difference of input, see (1), |
–55°C, 25°C, 125°C | 0.5 | 1.3 | V | |
| VCM | Common-mode voltage (CLKn, CLKn) | DC offset relative to VEE | –55°C, 25°C, 125°C | VEE + 1 | –0.3 | V | |
| VOH | High-level output voltage | IOH = –21 mA | –55°C | –1.26 | –0.85 | V | |
| 25°C | –1.2 | –0.85 | |||||
| 125°C | –1.15 | –0.8 | |||||
| VOL | Low-level output voltage | IOL = –5 mA | 25°C | –1.85 | –1.425 | V | |
| –55°C, 125°C | –1.85 | –1.25 | |||||
| VOD | Differential output voltage swing | Terminated with 50 Ω to VCC – 2 V, see Figure 4 | –55°C, 25°C, 125°C | 350 | mV | ||
(1) VID minimum and maximum is required to maintain AC specifications, actual device function tolerates a minimum VID of 100 mV.
6.6 LVPECL DC Electrical Characteristics
Vsupply: VCC = 2.375 V to 3.8 V, VEE= 0 V over operating temperature range TJ = –55°C to 125°C (unless otherwise noted)| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| IEE | Supply internal current | Absolute value of current | –55°C, 25°C, 125°C | 30 | 85 | mA | |
| ICC | Output and internal supply current | All outputs terminated 50 Ω to VCC – 2 V | -55°C, 25°C | 385 | mA | ||
| 125°C | 405 | ||||||
| IIN | Input current | Includes pullup and pulldown resistors VIH = VCC, VIL= VCC – 2 V |
–55°C, 25°C, 125°C | –150 | 150 | μA | |
| VBB | Internally generated bias voltage | VCC = 3 V to 3.8 V, IBB= –0.2 mA | –55°C, 25°C, 125°C | VCC – 1.45 | VCC – 1.3 | VCC – 1.125 | V |
| VCC = 2.375 V to 2.75 V, IBB = –0.2 mA | –55°C, 25°C, 125°C | VCC – 1.3 | VCC – 1.25 | VCC – 1.1 | |||
| VIH | High-level input voltage (CLK_SEL) | –55°C, 25°C, 125°C | VCC – 1.165 | VCC – 0.88 | V | ||
| VIL | Low-level input voltage (CLK_SEL) | –55°C, 25°C, 125°C | VCC – 1.81 | VCC – 1.475 | V | ||
| VID | Input amplitude (CLKn, CLKn) | Difference of input, see (1), |
–55°C, 25°C, 125°C | 0.5 | 1.3 | V | |
| VCM | Common-mode voltage (CLKn, CLKn) |
DC offset relative to VEE | –55°C, 25°C, 125°C | 1 | VCC – 0.3 | V | |
| VOH | High-level output voltage |
IOH = –21 mA | –55°C | VCC – 1.26 | VCC – 0.85 | V | |
| 25°C | VCC – 1.2 | VCC – 0.85 | |||||
| 125°C | VCC – 1.15 | VCC – 0.8 | |||||
| VOL | Low-level output voltage |
IOL = –5 mA | 25°C | VCC – 1.85 | VCC – 1.425 | V | |
| –55°C, 125°C | VCC – 1.85 | VCC – 1.25 | |||||
| VOD | Differential output voltage swing |
Terminated with 50 Ω to VCC – 2 V, see Figure 4 |
–55°C, 25°C, 125°C | 350 | mV | ||
(1) VID minimum and maximum is required to maintain ac specifications, actual device function tolerates a minimum VID of 100 mV.
6.7 AC Electrical Characteristics
Vsupply: VCC = 2.375 V to 3.8 V, VEE = 0 V or LVECL/LVPECL input VCC = 0 V, VEE = –2.375 V to –3.8 V over operating temperature range TJ = –55°C to 125°C (unless otherwise noted)| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| tpd | Differential propagation delay CLKn, CLKn to all Q0, Q0… Q9, Q9 | See note D in Figure 2 | 100 | 355 | ps | |
| tsk(o) | Output-to-output skew | See notes A and D in Figure 2 | 15 | 50 | ps | |
| tsk(pp) | Part-to-part skew | See notes B and D in Figure 2 | 70 | ps | ||
| taj | Additive phase jitter(1) | Integration bandwidth of 20 kHz to 20 MHz, fout = 200 MHz at 25°CC |
0.125 | 0.8 | ps | |
| f(max) | Maximum frequency(1) | Functional up to 3.5 GHz, see Figure 4 | 3500 | MHz | ||
| tr/tf | Output rise and fall time (20%, 80%) | See note D in Figure 2 | 240 | ps | ||
(1) Specified by bench characterization and is not tested in production.
1. See data sheet for absolute maximum and minimum recommended operating conditions.
2. Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect life).
Figure 1. CDCLVP111-SP Operating Life Derating Chart
A. Output skew is calculated as the greater of: the difference between the fastest and the slowest tPLHn (n = 0, 1,...9) or the difference between the fastest and the slowest tPHLn (n = 0, 1,...9).
B. Part-to-part skew, is calculated as the greater of: The difference between the fastest and the slowest tPLHn (n = 0, 1,...9) across multiple devices or the difference between the fastest and the slowest tPHLn (n = 0, 1,...9) across multiple devices.
C. Typical value measured at ambient when clock input is 155.52 MHz for an integration bandwidth of 20 kHz to 5 MHz.
D. Input conditions: VCM = 1 V, VID = 0.5 V and FIN = 1 GHz.
Figure 2. Waveform for Calculating Both Output and Part-to-Part Skew
See Interfacing Between LVPECL, LVDS, and CML (SCAA056).
Figure 3. Typical Termination for Output Driver
6.8 Typical Characteristics
| Differential Output Voltage Swing vs Frequency | ||||
| VCC = 2.375 V | VCM = 1 V | VID = 0.5 V | ||
7 Detailed Description
7.1 Overview
The CDCLVP111-SP is an open emitter for LVPECL outputs. Therefore, proper biasing and termination are required to ensure correct operation of the device and to minimize signal integrity. The proper termination for LVPECL outputs is 50 Ω to (VCC – 2), but this DC voltage is not readily available on PCB. Therefore, a Thevenin equivalent circuit is worked out for the LVPECL termination in both direct-coupled (DC) and AC-coupled configurations. These configurations are shown in Figure 6 (a and b) for VCC = 2.5 V and Figure 7 (a and b) for VCC = 3.3 V, respectively. TI recommends to place all resistive components close to either the driver end or the receiver end. If the supply voltage for the driver and receiver is different, AC coupling is required.
7.2 Functional Block Diagram
7.3 Feature Description
The CDCLVP111-SP is a low-additive jitter universal to LVPECL fan out buffer with 2 selectable inputs. The small package, low-output skew, and low-additive jitter make for a flexible device in demanding applications.
7.4 Device Functional Modes
Select input terminal by CLK_SEL pin.
Table 1. Function Table
| CLK_SEL | ACTIVE CLOCK INPUT |
|---|---|
| 0 | CLK0, CLK0 |
| 1 | CLK1, CLK1 |
The two inputs of the CDCLVP111-SP are internally mixed together and can be selected through the control pin. Unused inputs and outputs can be left floating to reduce overall component cost. Both AC and DC coupling schemes can be used with the CDCLVP111-SP to provide greater system flexibility.
