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  • CSD17313Q2 30-V N-Channel NexFET™ Power MOSFET

    • SLPS260E March   2010  – September 2015 CSD17313Q2

      PRODUCTION DATA.  

  • CONTENTS
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  • CSD17313Q2 30-V N-Channel NexFET™ Power MOSFET
  1. 1Features
  2. 2Applications
  3. 3Description
  4. 4Revision History
  5. 5 Specifications
    1. 5.1 Electrical Characteristics
    2. 5.2 Thermal Characteristics
    3. 5.3 Typical MOSFET Characteristics
  6. 6Device and Documentation Support
    1. 6.1 Community Resources
    2. 6.2 Trademarks
    3. 6.3 Electrostatic Discharge Caution
    4. 6.4 Glossary
  7. 7Mechanical, Packaging, and Orderable Information
    1. 7.1 Q2 Package Dimensions
    2. 7.2 Recommended PCB Pattern
    3. 7.3 Recommended Stencil Pattern
    4. 7.4 Q2 Tape and Reel Information
  8. IMPORTANT NOTICE

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DATA SHEET

CSD17313Q2 30-V N-Channel NexFET™ Power MOSFET

1 Features

  • Optimized for 5-V Gate Drive
  • Ultra-Low Qg and Qgd
  • Low Thermal Resistance
  • Pb-Free
  • RoHS Compliant
  • Halogen-Free
  • SON 2-mm × 2-mm Plastic Package

2 Applications

  • DC-DC Converters
  • Battery and Load Management Applications

3 Description

This 30-V, 24-mΩ, 2-mm x 2-mm SON NexFET™ power MOSFET is designed to minimize losses in power conversion applications and optimized for 5-V gate drive applications. The 2-mm × 2-mm SON offers excellent thermal performance for the size of the package.

Top View
CSD17313Q2 P0108-01_LPS235.gif

Added text for spacing

^^

Product Summary

TA = 25°C TYPICAL VALUE UNIT
VDS Drain-to-Source Voltage 30 V
Qg Gate Charge Total (4.5 V) 2.1 nC
Qgd Gate Charge Gate-to-Drain 0.4 nC
RDS(on) Drain-to-Source On Resistance VGS = 3 V 31 mΩ
VGS = 4.5 V 26 mΩ
VGS = 8 V 24 mΩ
VGS(th) Threshold Voltage 1.3 V

Ordering Information(1)

PART NUMBER QTY MEDIA PACKAGE SHIP
CSD17313Q2 3000 13-Inch Reel SON 2-mm × 2-mm Plastic Package Tape and Reel
CSD17313Q2T 250 7-Inch Reel
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Absolute Maximum Ratings

TA = 25°C VALUE UNIT
VDS Drain-to-Source Voltage 30 V
VGS Gate-to-Source Voltage +10 / –8 V
ID Continuous Drain Current (package limited) 5 A
Continuous Drain Current (silicon limited), TC = 25°C 19
Continuous Drain Current(1) 7.3
IDM Pulsed Drain Current, TA = 25°C(2) 57 A
PD Power Dissipation(1) 2.4 W
Power Dissipation, TC = 25°C 17
TJ,
TSTG 		Operating Junction and
Storage Temperature Range		 –55 to 150 °C
EAS Avalanche Energy, Single Pulse,
ID = 19A, L = 0.1mH, RG = 25Ω		 18 mJ
  1. Typical RθJA = 53°C/W on a 1-inch2, 2-oz. Cu pad on a
    0.06-inch thick FR4 PCB.
  2. Max RθJC = 7.4°C/W, pulse duration ≤100 μs, duty cycle ≤1%.

On State Resistance vs Gate to Source Voltage

CSD17313Q2 D007_SLPS260.gif

Gate Charge

CSD17313Q2 D004_SLPS260_FP.gif

4 Revision History

Changes from D Revision (March 2013) to E Revision

  • Added part number to title Go
  • Enhanced descriptionGo
  • Added 7-inch reel to Ordering Information table Go
  • Updated Continuous Drain Current Go
  • Updated pulsed current conditions Go
  • Updated Figure 1 to show RθJC curves Go
  • Added VGS = 4.5 V line in Figure 8 Go
  • Updated the SOA in Figure 10 Go
  • Added Community Resources Go
  • Added Device and Documentation section. Go

Changes from C Revision (January 2013) to D Revision

  • Changed Figure 10, Maximum Safe Operating AreaGo

Changes from B Revision (October 2010) to C Revision

  • Changed the Recommended PCB PatternGo
  • Added the Recommended Stencil PatternGo

Changes from A Revision (March 2010) to B Revision

  • Deleted the Package Marking Information sectionGo

Changes from * Revision (March 2010) to A Revision

  • Changed Qrr - Reverse Recovery Charge From: 10.2 nC To: 6.4 nCGo

5 Specifications

5.1 Electrical Characteristics

TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC CHARACTERISTICS
BVDSS Drain-to-source voltage VGS = 0 V, ID = 250 μA 30 V
IDSS Drain-to-source leakage VGS = 0 V, VDS = 24 V 1 μA
IGSS Gate-to-source leakage VDS = 0 V, VGS = +10 / –8 V 100 nA
VGS(th) Gate-to-source threshold voltage VDS = VGS, ID = 250 μA 0.9 1.3 1.8 V
RDS(on) Drain-to-source on resistance VGS = 3 V, ID = 4 A 31 42 mΩ
VGS = 4.5 V, ID = 4 A 26 32 mΩ
VGS = 8 V, ID = 4 A 24 30 mΩ
gfs Transconductance VDS = 15 V, ID = 4 A 16 S
DYNAMIC CHARACTERISTICS
Ciss Input capacitance VGS = 0 V, VDS = 15 V,
ƒ = 1 MHz		 260 340 pF
Coss Output capacitance 140 180 pF
Crss Reverse transfer capacitance 13 17 pF
RG Series gate resistance 1.3 2.6 Ω
Qg Gate charge total (4.5 V) VDS = 15 V,
ID = 4 A		 2.1 2.7 nC
Qgd Gate charge – gate-to-drain 0.4 nC
Qgs Gate charge – gate-to-source 0.7 nC
Qg(th) Gate charge at Vth 0.3 nC
Qoss Output charge VDS = 13.5 V, VGS = 0 V 3.8 nC
td(on) Turn on delay time VDS = 15 V, VGS = 4.5 V,
ID = 4 A, RG = 2 Ω		 2.8 ns
tr Rise time 3.9 ns
td(off) Turn off delay time 4.2 ns
tf Fall time 1.3 ns
DIODE CHARACTERISTICS
VSD Diode forward voltage ISD = 4 A, VGS = 0 V 0.85 1 V
Qrr Reverse recovery charge VDD= 13.5 V, IF = 4 A,
di/dt = 300 A/μs		 6.4 nC
trr Reverse recovery time 12.9 ns

5.2 Thermal Characteristics

TA = 25°C (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
RθJC Thermal resistance junction-to-case(1) 7.4 °C/W
RθJA Thermal resistance junction-to-ambient(1)(2) 67 °C/W
(1) RθJC is determined with the device mounted on a 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu pad on a 1.5 inch × 1.5 inch (3.81 cm × 3.81 cm), 0.06 inch (1.52 mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design.
(2) Device mounted on FR4 material with 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu.
CSD17313Q2 M0179-01_LPS260.gif
Max RθJA = 67°C/W when mounted on 1-inch2 (6.45-cm2) of 2-oz. (0.071-mm thick) Cu.
CSD17313Q2 M0180-01_LPS260.gif
Max RθJA = 228°C/W when mounted on a minimum pad area of 2-oz. (0.071-mm thick) Cu.

5.3 Typical MOSFET Characteristics

TA = 25°C (unless otherwise noted)
CSD17313Q2 D001_SLPS260.png
Figure 1. Transient Thermal Impedance
CSD17313Q2 D002_SLPS260_r2.gif
Figure 2. Saturation Characteristics
CSD17313Q2 D004_SLPS260.gif
ID = 4 A VDS = 15 V
Figure 4. Gate Charge
CSD17313Q2 D006_SLPS260.gif
ID = 250 µA
Figure 6. Threshold Voltage vs Temperature
CSD17313Q2 D008_SLPS260.gif
ID = 4 A
Figure 8. Normalized On-State Resistance vs Temperature
CSD17313Q2 D010_SLPS260_r2.gif
Single Pulse, Max RθJC = 7.4°C/W
Figure 10. Maximum Safe Operating Area
CSD17313Q2 D003_SLPS260.gif
VDS = 5 V
Figure 3. Transfer Characteristics
CSD17313Q2 D005_SLPS260.gif
Figure 5. Capacitance
CSD17313Q2 D007_SLPS260.gif
ID = 4 A
Figure 7. On-State Resistance vs Gate-to-Source Voltage
CSD17313Q2 D009_SLPS260.gif
Figure 9. Typical Diode Forward Voltage
CSD17313Q2 D011_SLPS260.gif
Figure 11. Single Pulse Unclamped Inductive Switching
CSD17313Q2 D012_SLPS260.gif
Figure 12. Maximum Drain Current vs Temperature

6 Device and Documentation Support

6.1 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

    TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.
    Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

6.2 Trademarks

NexFET, E2E are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

6.3 Electrostatic Discharge Caution

esds-image

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

6.4 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

7 Mechanical, Packaging, and Orderable Information

7.1 Q2 Package Dimensions

CSD17313Q2 M0175-02_LPS260.gif
DIM MILLIMETERS INCHES
MIN NOM MAX MIN NOM MAX
A 0.700 0.750 0.800 0.028 0.030 0.032
A1 0.000 0.050 0.000 0.002
b 0.250 0.300 0.350 0.010 0.012 0.014
C 0.203 TYP 0.008 TYP
D 2.000 TYP 0.080 TYP
D1 0.900 0.950 1.000 0.036 0.038 0.040
D2 0.300 TYP 0.012 TYP
E 2.000 TYP 0.080 TYP
E1 0.900 1.000 1.100 0.036 0.040 0.044
E2 0.280 TYP 0.0112 TYP
E3 0.470 TYP 0.0188 TYP
e 0.650 BSC 0.026 TYP
K 0.280 TYP 0.0112 TYP
K1 0.350 TYP 0.014 TYP
K2 0.200 TYP 0.008 TYP
K3 0.200 TYP 0.008 TYP
K4 0.470 TYP 0.0188 TYP
L 0.200 0.25 0.300 0.008 0.010 0.012

7.2 Recommended PCB Pattern

CSD17313Q2 Recommended_PCB_Pattern.png

For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing through PCB Layout Techniques.

7.3 Recommended Stencil Pattern

CSD17313Q2 Recommended_Stencil_Pattern.png

NOTE:

All dimensions are in mm, unless otherwise specified.

7.4 Q2 Tape and Reel Information

CSD17313Q2 M0168-01_LPS235.gif

NOTES:

1. Measured from centerline of sprocket hole to centerline of pocket
2. Cumulative tolerance of 10 sprocket holes is ±0.20
3. Other material available
4. Typical SR of form tape Max 108 OHM/SQ
5. All dimensions are in mm, unless otherwise specified.

 
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