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The DAC8532 is a dual channel, 16-bit digital-to-analog converter (DAC) offering low power operation and a flexible serial host interface. Each on-chip precision output amplifier allows rail-to-rail output swing to be achieved over the supply range of 2.7 V to 5.5 V. The device supports a standard 3-wire serial interface capable of operating with input data clock frequencies up to 30 MHz for VDD = 5 V.
The DAC8532 requires an external reference voltage to set the output range of each DAC channel. The device incorporates a power-on reset circuit which ensures that the DAC outputs power up at zero-scale and remain there until a valid write takes place. The DAC8532 provides a flexible power-down feature, accessible over the serial interface, that reduces the current consumption of the device to 200 nA at 5 V.
The low-power consumption of the device in normal operation makes it ideally suited to portable battery-operated equipment and other low-power applications. The power consumption is 2.5 mW at 5 V, reducing to 1 µW in power-down mode.
The DAC8532 is available in a VSSOP-8 package with a specified operating temperature range of –40°C to 105°C.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
DAC8532 | VSSOP (8) | 3.00 mm × 3.00 mm |
Changes from A Revision (May 2003) to B Revision
Changes from * Revision (December 2001) to A Revision
PIN | NAME | FUNCTION |
---|---|---|
1 | VDD | Power supply input, 2.7 V to 5.5 V |
2 | VREF | Reference voltage input |
3 | VOUTB | Analog output voltage from DAC B |
4 | VOUTA | Analog output voltage from DAC A |
5 | SYNC | Level triggered SYNC input (active LOW). This is the frame synchronization signal for the input data. When SYNC goes LOW, it enables the input shift register and data is transferred on the falling edges of SCLK. The action specified by the 8-bit control byte and 16-bit data word is executed following the 24th falling SCLK clock edge (unless SYNC is taken HIGH before this edge in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC8532). |
6 | SCLK | Serial Clock Input. Data can be transferred at rates up to 30 MHz at 5 V. |
7 | DIN | Serial Data Input. Data is clocked into the 24-bit input shift register on the falling edge of the serial clock input. |
8 | GND | Ground reference point for all circuitry on the part. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VDD to GND | –0.3 | 6 | V | |
Digital input voltage to GND | –0.3 | VDD+0.3 | ||
VOUTA or VOUTB to GND | –0.3 | VDD+0.3 | ||
Operating temperature range | –40 | 105 | °C | |
TJ | 150 |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
Tstg | Storage temperature range | –65 | 150 | °C | |
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | 1000 | V | |
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | 500 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VDD to GND | 0 | 5.5 | V | ||
Digital input voltage to GND | 0 | VDD | |||
VOUTA or VOUTB to GND | 0 | VDD | |||
Operating temperature range | –40 | 105 | °C |
THERMAL METRIC(1) | DAC8532 | UNIT | |
---|---|---|---|
DGK | |||
8 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 164.0 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 59.4 | |
RθJB | Junction-to-board thermal resistance | 84.8 | |
ψJT | Junction-to-top characterization parameter | 6.5 | |
ψJB | Junction-to-board characterization parameter | 83.3 | |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | n/a |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
STATIC PERFORMANCE(1) | |||||
Resolution | 16 | Bits | |||
Relative accuracy | ±0.0987 | % of FSR | |||
Differential nonlinearity | 16-bit monotonic | ±1 | LSB | ||
Zero code error | 5 | 25 | mV | ||
Full-scale error | –0.15 | –1 | % of FSR | ||
Gain error | ±1 | % of FSR | |||
Zero code error drift | ±20 | µV/°C | |||
Gain temperature coefficient | ±5 | ppm of FSR/°C | |||
Channel-to-channel matching PSRR | RL = 2 kΩ, CL = 200 pF | 15 | mV | ||
0.75 | mV/V | ||||
OUTPUT CHARACTERISTICS(2) | |||||
Output voltage range | 0 | VREF | V | ||
Output voltage settling time | To ±0.003% FSR 0200H to FD00H, RL = 2 kΩ; 0 pF < CL < 200 pF, RL = 2 kΩ; CL = 500 pF |
8 | 10 | µs | |
12 | |||||
Slew rate | 1 | V/µs | |||
Capacitive load stability | RL = ∞ | 470 | pF | ||
RL = 2 kΩ | 1000 | ||||
Code change glitch impulse | 1 LSB change around major carry | 20 | nV-s | ||
Digital feedthrough | 0.5 | nV-s | |||
DC crosstalk | 0.25 | LSB | |||
AC crosstalk | –100 | –96 | dB | ||
DC output impedance | 1 | Ω | |||
Short circuit current | VDD = 5 V | 50 | mA | ||
VDD = 3 V | 20 | ||||
Power-up time | Coming out of power-down mode VDD = 5 V | 2.5 | µs | ||
Coming out of power-down mode VDD = 3 V | 5 | µs | |||
AC PERFORMANCE | |||||
SNR | BW = 20 kHz, VDD = 5 V, FOUT = 1 kHz, 1st 19 harmonics removed |
94 | dB | ||
THD | 67 | ||||
SFDR | 69 | ||||
SINAD | 65 | ||||
REFERENCE INPUT | |||||
Reference current | VREF = VDD = 5 V | 67 | 90 | µA | |
VREF = VDD = 3 V | 40 | 54 | |||
Reference input range | 0 | VDD | V | ||
Reference input impedance | 75 | kΩ | |||
LOGIC INPUTS (2) | |||||
Input current | ±1 | µA | |||
VINL, Input LOW voltage | VDD = 5 V | 0.8 | V | ||
VDD = 3 V | 0.6 | ||||
VINH, Input HIGH voltage | VDD = 5 V | 2.4 | V | ||
VDD = 3 V | 2.1 | ||||
Pin capacitance | 3 | pF | |||
POWER REQUIREMENTS | |||||
VDD | 2.7 | 5.5 | V | ||
IDD (normal mode) | DAC active and excluding load current | ||||
VDD = 3.6 V to 5.5 V | VIH = VDD and VIL = GND | 500 | 800 | µA | |
VDD = 2.7 V to 3.6 V | 450 | 750 | |||
IDD (all power-down modes) | |||||
VDD = 3.6 V to 5.5 V | VIH = VDD and VIL = GND | 0.2 | 1 | µA | |
VDD = 2.7 V to 3.6 V | 0.05 | 1 | |||
POWER EFFICIENCY | |||||
IOUT/IDD | ILOAD = 2 mA, VDD = 5 V | 89% | |||
TEMPERATURE RANGE | |||||
Specified performance | –40 | 105 | °C |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
t1(3) | SCLK cycle time | VDD = 2.7 V to 3.6 V | 50 | ns | ||
VDD = 3.6 V to 5.5 V | 33 | |||||
t2 | SCLK HIGH time | VDD = 2.7 V to 3.6 V | 13 | ns | ||
VDD = 3.6 V to 5.5 V | 13 | |||||
t3 | SCLK LOW time | VDD = 2.7 V to 3.6 V | 22.5 | ns | ||
VDD = 3.6 V to 5.5 V | 13 | |||||
t4 | SYNC to SCLK rising edge setup time | VDD = 2.7 V to 3.6 V | 0 | ns | ||
VDD = 3.6 V to 5.5 V | 0 | |||||
t5 | Data setup time | VDD = 2.7 V to 3.6 V | 5 | ns | ||
VDD = 3.6 V to 5.5 V | 5 | |||||
t6 | Data hold time | VDD = 2.7 V to 3.6 V | 4.5 | ns | ||
VDD = 3.6 V to 5.5 V | 4.5 | |||||
t7 | 24th SCLK falling edge to SYNC rising edge | VDD = 2.7 V to 3.6 V | 0 | ns | ||
VDD = 3.6 V to 5.5 V | 0 | |||||
t8 | Minimum SYNC HIGH time | VDD = 2.7 V to 3.6 V | 50 | ns | ||
VDD = 3.6 V to 5.5 V | 33 | |||||
t9 | 24th SCLK falling edge to SYNC falling edge | VDD = 2.7 V to 5.5 V | 100 | ns |