SNLS407D April   2012  – October 2014 DS90UB925Q-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 AC Electrical Characteristics
    7. 6.7 Recommended Timing for the Serial Control Bus
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Charateristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High Speed Forward Channel Data Transfer
      2. 7.3.2  Low Speed Back Channel Data Transfer
      3. 7.3.3  Backward Compatible Mode
      4. 7.3.4  Common Mode Filter Pin (CMF)
      5. 7.3.5  Video Control Signal Filter
      6. 7.3.6  EMI Reduction Features
        1. 7.3.6.1 Input SSC Tolerance (SSCT)
      7. 7.3.7  LVCMOS VDDIO Option
      8. 7.3.8  Power Down (PDB)
      9. 7.3.9  Remote Auto Power Down Mode
      10. 7.3.10 Input PCLK Loss Detect
      11. 7.3.11 Serial Link Fault Detect
      12. 7.3.12 Pixel Clock Edge Select (RFB)
      13. 7.3.13 Low Frequency Optimization (LFMODE)
      14. 7.3.14 Interrupt Pin — Functional Description And Usage (INTB)
      15. 7.3.15 Internal Pattern Generation
      16. 7.3.16 GPIO[3:0] and GPO_REG[8:4]
        1. 7.3.16.1 GPIO[3:0] Enable Sequence
        2. 7.3.16.2 GPO_REG[8:4] Enable Sequence
      17. 7.3.17 I2S Transmitting
        1. 7.3.17.1 Secondary I2S Channel
      18. 7.3.18 Built In Self Test (BIST)
        1. 7.3.18.1 BIST Configuration and Status
          1. 7.3.18.1.1 Sample BIST Sequence
        2. 7.3.18.2 Forward Channel And Back Channel Error Checking
    4. 7.4 Device Functional Modes
      1. 7.4.1 Configuration Select (MODE_SEL)
      2. 7.4.2 Repeater Application
        1. 7.4.2.1 Repeater Configuration
        2. 7.4.2.2 Repeater Connections
    5. 7.5 Programming
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power Up Requirements and PDB Pin
    2. 9.2 CML Interconnect Guidelines
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

1 Features

  • Bidirectional Control Interface Channel Interface with I2C Compatible Serial Control Bus
  • Supports High Definition (720 p) Digital Video Format
  • RGB888 + VS, HS, DE and I2S Audio Supported
  • Supports Two 10–bit Camera Video Streams
  • 5 – 85MHz PCLK Supported
  • Single 3.3 V Operation with 1.8 V or 3.3 V Compatible LVCMOS I/O Interface
  • AC-Coupled STP Interconnect Up to 10 Meters
  • Parallel LVCMOS Video Inputs
  • DC-Balanced and Scrambled Data with Embedded Clock
  • Supports Repeater Application
  • Internal Pattern Generation
  • Low Power Modes Minimize Power Dissipation
  • Automotive Grade Product: AEC-Q100 Grade 2 Qualified
  • >8kV HBM and ISO 10605 ESD Rating
  • Backward Compatible to FPD-Link II

2 Applications

  • Automotive Display for Navigation
  • Rear Seat Entertainment Systems
  • Automotive Driver Assistance
  • Automotive Megapixel Camera Systems

3 Description

The DS90UB925Q-Q1 serializer, in conjunction with the DS90UB926Q-Q1 deserializer, provides a complete digital interface for concurrent transmission of high-speed video, audio, and control data for automotive display and image sensing applications.

The chipset is ideally suited for automotive video-display systems with HD formats and automotive vision systems with megapixel resolutions. The DS90UB925Q-Q1 incorporates an embedded bidirectional control channel and low latency GPIO controls. This chipset translates a parallel interface into a single pair high-speed serialized interface. The serial bus scheme, FPD-Link III, supports full duplex of high-speed video data transmission and bidirectional control communication over a single differential link. Consolidation of video data and control over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design.

The DS90UB925Q-Q1 serializer embeds the clock, DC scrambles & balances the data payload, and level shifts the signals to high-speed low voltage differential signaling. Up to 24 data bits are serialized along the video control signals.

Serial transmission is optimized by a user selectable de-emphasis. EMI is minimized by the use of low voltage differential signaling, data scrambling and randomization and spread spectrum clocking compatibility.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
DS90UB925Q-Q1 WQFN (48) 7.00 mm × 7.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.
30143327.gif