DLPA078B February 2017 – September 2021 DLP160AP , DLP160CP , DLP2000 , DLP2010 , DLP230GP , DLP230KP , DLP230NP , DLP3010 , DLP3310 , DLP4710 , DLP471TP , DLPC3420 , DLPC3421
The interface between the DLPC343x controller and the DMD consists of four single ended control signals and a sub-LVDS bus consisting of 4 or 8 (depending on the DMD) data pairs and a clock pair. The differential signals make up the HS (high speed) bus that sends mirror on/off data to the DMD. Three of the four control lines (LS_CLK, LS_WDATA and LS_RDATA) make up a serial control bus. While the fourth line (ARSTZ) is a power up reset.