DLPU078A july 2019 – may 2023 DLP230NP , DLPC3436
MSB | Byte 1 | LSB | |||||
---|---|---|---|---|---|---|---|
b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
Bit | Type | Description |
---|---|---|
7-3 | R | Reserved |
2-0 | W |
Input Source 0h = Test Pattern Generator from XPR FPGA 1h = External Parallel Video from XPR FPGA 2h = FPD-Link or LVDS Source from XPR FPGA 3h = Internal Controller Splash Screen 4h = Internal Controller Test Pattern 5h - 7h = Reserved |
MSB | Byte 2 | LSB | |||||
---|---|---|---|---|---|---|---|
b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
Bit | Type | Description |
---|---|---|
7-1 | R | Reserved |
0 | W |
External Calibration Setting 0h = External Calibration Disabled 1h = External Calibration Enabled |