DLPU103B october 2020 – may 2023 DLP230NP
Table 9-2 provides a list of the assigned GPIO configurations for each operating mode on the DLPDLCR230NPEVM. The "Controller Flash Write" and "FPGA Flash Write" configurations are employed when using the "flash_write_controller.py" and "flash_write_fpga.py" scripts, respectively. All other scripts can and should use the default "DPI" configuration mode. In the cases where the GPIO pin should be driven by the Raspberry Pi, the particular pin is marked as (HIGH) or (LOW) in the "Pin Mode" column.
DPI Configuration (RGB666 Only) | Controller Flash Write Configuration | FPGA Flash Write Configuration | ||||
---|---|---|---|---|---|---|
Broadcom Pin Number (BCM) | Pin Mode | Pin Function | Pin Mode | Pin Function | Pin Mode | Pin Function |
0 | ALT2 | PCLK | OUT | N/A | OUT | N/A |
1 | ALT2 | DATAEN | IN | N/A | IN | N/A |
2 | ALT2 | VSYNC | IN | N/A | IN | N/A |
3 | ALT2 | HSYNC | IN | N/A | IN | N/A |
4 | ALT2 | B2 | IN | N/A | IN | N/A |
5 | ALT2 | B3 | IN | N/A | IN | N/A |
6 | ALT2 | B4 | IN | N/A | IN | N/A |
7 | ALT2 | B5 | IN | N/A | IN | N/A |
8 | ALT2 | B6 | OUT | SPI_CE0 | OUT | SPI_CE0 |
9 | ALT2 | B7 | ALT0 | SPI_MISO | ALT0 | SPI_MISO |
10 | ALT2 | G2 | ALT0 | SPI_MOSI | ALT0 | SPI_MOSI |
11 | ALT2 | G3 | ALT0 | SPI_SCLK | ALT0 | SPI_SCLK |
12 | ALT2 | G4 | IN | N/A | IN | N/A |
13 | ALT2 | G5 | IN | N/A | IN | N/A |
14 | ALT2 | G6 | IN | N/A | IN | N/A |
15 | ALT2 | G7 | IN | N/A | IN | N/A |
16 | ALT2 | R2 | IN | N/A | IN | N/A |
17 | ALT2 | R3 | IN | N/A | IN | N/A |
18 | ALT2 | R4 | IN | N/A | IN | N/A |
19 | ALT2 | R5 | IN | N/A | IN | N/A |
20 | ALT2 | R6 | IN | N/A | IN | N/A |
21 | ALT2 | R7 | IN | N/A | IN | N/A |
22 | OUT | I2C-SCL | IN | N/A | IN | N/A |
23 | OUT | I2C-SDA | IN | N/A | IN | N/A |
24 | IN | SPI_SEL_ASIC | OUT (HIGH) | SPI_SEL_ASIC | IN | SPI_SEL_ASIC |
25 | OUT (HIGH) | MODE_SEL | IN | MODE_SEL | IN | MODE_SEL |
26 | IN | PROJ_ON | OUT (HIGH) | PROJ_ON | OUT (HIGH) | PROJ_ON |
27 | IN | SPI_SEL_FPGA | IN | SPI_SEL_FPGA | OUT (HIGH) | SPI_SEL_FPGA |
A brief summary of pin functions used follows:
Do not attempt to enable SPI functionality or drive SPI_SEL_ASIC or SPI_SEL_FPGA enable pins while DPI video output is active. Enabling access to the SPI bus (and thereby controller/FPGA flash devices) while DPI video output is active may inadvertently erase or corrupt the onboard flash memory of the DLPDLCR230NPEVM.
When writing to the flash device, only ONE of either the "SPI_SEL_ASIC" or "SPI_SEL_FPGA" lines should be active, or driven high at a time. Attempting to drive both SPI select lines can lead to hardware failure during the flash write operation.