JAJS012J October   2004  – November 2018 TPS75003

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーションの回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
      1. 6.6.1 Buck Converter
      2. 6.6.2 LDO Converter
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Operation (Buck Controllers)
      2. 7.3.2  Enable (Buck Controllers)
      3. 7.3.3  UVLO (Buck Controllers)
      4. 7.3.4  Current Limit (Buck Controllers)
      5. 7.3.5  Short-Circuit Protection (Buck Controllers)
      6. 7.3.6  Soft-Start (Buck Controllers)
      7. 7.3.7  LDO Operation
      8. 7.3.8  Internal Current Limit (LDO)
      9. 7.3.9  Enable Pin (LDO)
      10. 7.3.10 Dropout Voltage (LDO)
      11. 7.3.11 Transient Response (LDO)
      12. 7.3.12 Thermal Protection (LDO)
      13. 7.3.13 Power Dissipation (LDO)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Input Capacitor CIN1, CIN2 Selection (Buck Controllers)
        2. 8.2.2.2  Inductor Value Selection (Buck Controllers)
        3. 8.2.2.3  External PMOS Transistor Selection (Buck Controllers)
        4. 8.2.2.4  Diode Selection (Buck Controllers)
        5. 8.2.2.5  Output Capacitor Selection (Buck Controllers)
        6. 8.2.2.6  Output Voltage Ripple Effect on VOUT (Buck Controllers)
        7. 8.2.2.7  Soft-Start Capacitor Selection (Buck Controllers)
        8. 8.2.2.8  Output Voltage Setting Selection (Buck Controllers)
        9. 8.2.2.9  Input Capacitor Selection (LDO)
        10. 8.2.2.10 Output Capacitor Selection (LDO)
        11. 8.2.2.11 Soft-Start Capacitor Selection (LDO)
        12. 8.2.2.12 Setting Output Voltage (LDO)
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PCB Layout Considerations
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 11.1.2 開発サポート
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

9 Power Supply Recommendations

There are three separate blocks internal to the TPS75003 device: two identical buck controllers and one integrated LDO regulator. The input voltage, VINX, to the IN1 and IN2 pins must be within the range specified in the Electrical Characteristics and must be greater than the nominal output voltage of BUCK1 or BUCK2, respectively. However, the maximum output voltages, VOUT1 and VOUT2, are determined by external component selection and cannot be specified. The input voltage to the LDO regulator, VIN3, must be greater than the drop-out voltage (VDO) added to VOUT3 or an absolute value of 2.2 V, whichever is greater. The power supply into the IN1, IN2, and IN3 pins do not need to be equal to each other but all of the design values must adhere to the minimum and maximum specifications of the TPS75003 and external components. Other considerations are based on the relationship of pins used inside the TPS75003 device.

The power supply into IN1 is used as the power supply to drive the gate of the switch connected at SW1. The difference between the voltages at the IN1 pin and IS1 pin is the input to the sensing which controls current limit. The power supply connected at IN1 must be the power supply connected to 33-mΩ sense resistor, and the opposite terminal of the sense resistor must connect directly to IS1 and the source pin(s) of the eternal PMOS FET.

Similarly, the power supply into IN2 is used as the power supply to drive the gate of the switch connected at SW2. The difference between the voltages at the IN2 pin and IS2 pin is the input to the sensing which controls current limit. The power supply connected at IN2 must be the power supply connected to 33-mΩ sense resistor, and the opposite terminal of the sense resistor must connect directly to IS2 and the source pins of the eternal PMOS FET.

The power supply into IN3 is used as the power supply to the LDO regulator and all internal support circuitry. Unlike the BUCK1 and BUCK2 controllers, the power does not bypass the TPS75003 device. Therefore, the output of the LDO is named OUT3 and up to 300-mA of current will go directly from IN3 to OUT3.