JAJS016Q August   2003  – September 2024 TPS732

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Thermal Information
    6. 5.6 Electrical Characteristics
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Output Noise
      2. 6.3.2 Internal Current Limit
      3. 6.3.3 Enable Pin and Shutdown
      4. 6.3.4 Dropout Voltage
      5. 6.3.5 Reverse Current
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation With 1.7V ≤ VIN ≤ 5.5V and VEN ≥ 1.7V
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Input and Output Capacitor Requirements
        2. 7.2.2.2 Transient Response
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Thermal Considerations
          1. 7.4.1.1.1 Power Dissipation
      2. 7.4.2 Layout Examples
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Evaluation Modules
        2. 8.1.1.2 Spice Models
      2. 8.1.2 Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 ドキュメントの更新通知を受け取る方法
    4. 8.4 サポート・リソース
    5. 8.5 Trademarks
    6. 8.6 静電気放電に関する注意事項
    7. 8.7 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

TPS732 DBV Package,5-Pin SOT-23(Top View)Figure 4-1 DBV Package,5-Pin SOT-23(Top View)
TPS732 DCQ Package,6-Pin SOT-223(Top View)Figure 4-3 DCQ Package,6-Pin SOT-223
(Top View)
TPS732 DRB Package,8-Pin VSON With Exposed Thermal Pad(Top View)Figure 4-2 DRB Package,8-Pin VSON With Exposed Thermal Pad(Top View)
Table 4-1 Pin Functions
PIN TYPE DESCRIPTION
NAME NO.
SOT-23 SOT-223 VSON
IN 1 1 8 I Input supply.
GND 2 3, 6 4, Pad — Ground.
EN 3 5 5 I Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdown mode. See the Enable Pin and Shutdown section under Feature Description for more details. Connect EN to IN if not used.
NR 4 4 3 — Fixed voltage versions only—connecting an external capacitor to this pin bypasses noise generated by the internal band gap, reducing output noise to very low levels.
FB 4 4 3 I Adjustable voltage version only—this pin is the input to the control loop error amplifier, and is used to set the output voltage of the device.
OUT 5 2 1 O Output of the regulator. There are no output capacitor requirements for stability.