JAJS016Q August   2003  – September 2024 TPS732

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Thermal Information
    6. 5.6 Electrical Characteristics
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Output Noise
      2. 6.3.2 Internal Current Limit
      3. 6.3.3 Enable Pin and Shutdown
      4. 6.3.4 Dropout Voltage
      5. 6.3.5 Reverse Current
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation With 1.7V ≤ VIN ≤ 5.5V and VEN ≥ 1.7V
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Input and Output Capacitor Requirements
        2. 7.2.2.2 Transient Response
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Thermal Considerations
          1. 7.4.1.1.1 Power Dissipation
      2. 7.4.2 Layout Examples
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Evaluation Modules
        2. 8.1.1.2 Spice Models
      2. 8.1.2 Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 ドキュメントの更新通知を受け取る方法
    4. 8.4 サポート・リソース
    5. 8.5 Trademarks
    6. 8.6 静電気放電に関する注意事項
    7. 8.7 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.5 Thermal Information

THERMAL METRIC(1)(2) TPS732 Legacy silicon(3) UNIT
DRB (VSON) DCQ (SOT-223) DBV (SOT-23)
8 PINS 6 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 58.3 53.1 205.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 93.8 35.2 119 °C/W
RθJB Junction-to-board thermal resistance 72.8 7.8 35.4 °C/W
ψJT Junction-to-top characterization parameter 2.7 2.9 12.7 °C/W
ψJB Junction-to-board characterization parameter 25 7.7 34.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 5 N/A N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note.
(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
(3) Thermal data for the DRB, DCQ, and DBV packages are derived by thermal simulations based on JEDEC-standard methodology as specified in the JESD51 series. The following assumptions are used in the simulations:
(a) i. DRB: The exposed pad is connected to the PCB ground layer through a 2x2 thermal via array.
 ii. DCQ: The exposed pad is connected to the PCB ground layer through a 3x2 thermal via array.
 iii. DBV: There is no exposed pad with the DBV package.
(b) i. DRB: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper coverage.
 ii. DCQ: Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage.
 iii. DBV: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper coverage.
(c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area. To understand the effects of the copper area on thermal performance, see the Power Dissipation section of this data sheet.