JAJS194E January   2007  – June 2019 TPS40077

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーション概略図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Electrical Characteristics
    5. 6.5 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Minimum Pulse Duration
      2. 7.3.2  Slew Rate Limit On VDD
      3. 7.3.3  Setting The Switching Frequency (Programming The Clock Oscillator)
      4. 7.3.4  Loop Compensation
      5. 7.3.5  Shutdown and Sequencing
      6. 7.3.6  Boost and LVBP Bypass Capacitance
      7. 7.3.7  Internal Regulators
      8. 7.3.8  Power Dissipation
      9. 7.3.9  Boost Diode
      10. 7.3.10 Synchronous Rectifier Control
    4. 7.4 Programming
      1. 7.4.1 Programming The Ramp Generator Circuit and UVLO
      2. 7.4.2 Programming Soft Start
      3. 7.4.3 Programming Short-Circuit Protection
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Buck Regulator 8-V to 16-V Input, 1.8-V Output at 10 A
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Power Train Components
            1. 8.2.1.2.1.1  Output Inductor, LOUT
            2. 8.2.1.2.1.2  Output Capacitor, COUT, ELCO and MLCC
            3. 8.2.1.2.1.3  Input Capacitor, CIN ELCO and MLCC
            4. 8.2.1.2.1.4  Switching MOSFET, QSW
            5. 8.2.1.2.1.5  Rectifier MOSFET, QSR
            6. 8.2.1.2.1.6  Timing Resistor, RT
            7. 8.2.1.2.1.7  Feed-Forward and UVLO Resistor, RKFF
            8. 8.2.1.2.1.8  Soft-Start Capacitor, CSS
            9. 8.2.1.2.1.9  Short-Circuit Protection, RILIM and CILIM
            10. 8.2.1.2.1.10 Boost Voltage, CBOOST and DBOOST (Optional)
            11. 8.2.1.2.1.11 Closing the Feedback Loop, RZ1, RP1, RPZ2, RSET1, RSET2, CZ2, CP2, and CPZ1
        3. 8.2.1.3 Application Curves
    3. 8.3 Additional System Examples
  9. 9 Layout
    1. 9.1 Layout Guidelines
  10. 10デバイスおよびドキュメントのサポート
    1. 10.1 デバイス・サポート
      1. 10.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 10.2 ドキュメントのサポート
      1. 10.2.1 関連資料
    3. 10.3 ドキュメントの更新通知を受け取る方法
    4. 10.4 コミュニティ・リソース
    5. 10.5 商標
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 Glossary
  11. 11メカニカル、パッケージ、および注文情報

6.4 Electrical Characteristics

TA = –40°C to 85°C, VIN = 12 Vdc, RT = 90.9 kΩ, IKFF = 300 μA, fSW = 500 kHz, and all parameters at zero power dissipation (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VVDD Input voltage range, VIN 4.5 28 V
IVDD Quiescent current Output drivers not switching 2.5 3.5 mA
VLVBP Output voltage TA = TJ = 25°C 3.9 4.2 4.5 V
OSCILLATOR/RAMP GENERATOR
fOSC Accuracy 450 500 550 kHz
VRAMP PWM ramp voltage(1) VPEAK – VVAL 2 V
VRT RT voltage 2.23 2.4 2.58 V
tON Minimum output pulse time(1) CHDRV = 0 nF 150 ns
Maximum duty cycle VFB = 0 V, 100 kHz ≤ fSW ≤ 500 kHz 84% 93%
VFB = 0 V, fSW = 1 MHz 76% 93%
VKFF Feed-forward voltage 0.35 0.4 0.45 V
IKFF Feed-forward current operating range(1) 20 1100 μA
SOFT START
ISS Charge current 7 12 17 μA
tDSCH Discharge time CSS = 3.9 nF 25 75 μs
tSS Soft-start time CSS = 3.9 nF, VSS rising from 0.7 V to 1.6 V 210 290 500 μs
VSSSD Turnon threshold 310 365 420 mV
Shutdown threshold 225 275 325
VSSSDH Shutdown threshold hysteresis 35 150 mV
VDBP Output voltage VDD > 10 V 7 8 9 V
VDD = 4.5 V, IOUT = 25 mA 4 4.3
ERROR AMPLIFIER
VFB Feedback regulation voltage total variation TJ = 25°C 0.698 0.7 0.704 V
0°C ≤ TJ ≤ 85°C 0.69 0.7 0.707
–40°C ≤ TJ ≤ 85°C 0.69 0.7 0.715
VSS Soft-start offset from VSS(1) Offset from VSS to error amplifier 1 V
GBW Gain bandwidth(1) 5 10 MHz
AVOL Open-loop gain 50 dB
ISRC Output source current 2.5 4.5 mA
ISINK Output sink current 2.5 6 mA
IBIAS Input bias current VFB = 0.7 V –250 0 nA
SHORT-CIRCUIT CURRENT PROTECTION
IILIM Current sink into current limit 80 105 125 μA
VILIM(ofst) Current limit offset voltage (VSW – VILIM) VILIM = 11.5 V, VVDD = 12 V –75 –50 –30 mV
tHSC Minimum HDRV pulse duration During short circuit 135 225 ns
Propagation delay to output(1) 50 ns
tBLANK Blanking time(1) 50 ns
tOFF Off time during a fault (SS cycle times) 7 Cycles
VSW Switching level to end precondition
(VVDD – VSW)(1) 		2 V
tPC Precondition time(1) 100 ns
VILIM Current limit precondition voltage threshold(1) 6.8 V
OUTPUT DRIVERS
tHFALL High-side driver fall time (HDRV – SW)(1) CHDRV = 2200 pF 36 ns
tHRISE High-side driver rise time (HDRV – SW)(1) 48 ns
tHFALL High-side driver fall time (HDRV – SW)(1) CHDRV = 2200 pF, VVDD = 4.5 V,
0.2 V ≤ VSS ≤ 4 V		 72 ns
tHRISE High-side driver rise time (HDRV – SW)(1) 96 ns
tLFALL Low-side driver fall time(1) CLDRV = 2200 pF 24 ns
tLRISE Low-side driver rise time(1) 48 ns
tLFALL Low-side driver fall time(1) CLDRV = 2200 pF, VVDD = 4.5 V,
0.2 V ≤ VSS ≤ 4 V		 48 ns
tLRISE Low-side driver rise time(1) 96 ns
VOH High-level output voltage, HDRV
(VBOOST – VHDRV)		 IHDRV = –0.01 A 0.7 1 V
IHDRV = –0.1 A 0.95 1.3
VOL Low-level output voltage, HDRV (VHDRV – VSW) IHDRV = 0.01A 0.06 0.1 V
IHDRV = 0.1 A 0.65 1
VOH High-level output voltage, LDRV
(VDBP – VLDRV)		 ILDRV= –0.01A 0.65 1 V
ILDRV = –0.1 A 0.875 1.2
VOL Low-level output voltage, LDRV ILDRV = 0.01 A 0.03 0.05 V
ILDRV = 0.1 A 0.3 0.5
VBOOST Output voltage VDD = 12 V 15.2 17 V
UVLO
VUVLO Programmable UVLO threshold voltage RKFF = 90.9 kΩ, turn-on, VVDD rising 6.2 7.2 8.2 V
Programmable UVLO hysteresis RKFF = 90.9 kΩ 1.1 1.55 2 V
Fixed UVLO threshold voltage Turn-on, VVDD rising 4.15 4.3 4.45 V
Fixed UVLO hysteresis 275 365 mV
POWER GOOD
VPG Power-good voltage IPG = 1 mA 370 500 mV
VOH High-level output voltage, FB 770 mV
VOL Low-level output voltage, FB 630 mV
THERMAL SHUTDOWN
Shutdown temperature threshold(1) 165 °C
Hysteresis(1) 15 °C
(1) Ensured by design. Not production tested.