JAJS219F December   2004  – March 2017 TPA2012D2

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Dissipation Rating Table
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Fixed Gain Setting
      2. 9.3.2 Short-Circuit Protection
      3. 9.3.3 Operation With DACs and CODECs
      4. 9.3.4 Filter-Free Operation and Ferrite Bead Filters
    4. 9.4 Device Functional Modes
      1. 9.4.1 Shutdown Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 TPA2012D2 With Differential Input Signal
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Surface Mount Capacitors
          2. 10.2.1.2.2 Decoupling Capacitor (CS)
          3. 10.2.1.2.3 Input Capacitors (CI)
        3. 10.2.1.3 Application Curves
      2. 10.2.2 TPA2012D2 With Single-Ended Input Signal
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Power Supply Decoupling Capacitor
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Pad Side
      2. 12.1.2 Component Location
      3. 12.1.3 Trace Width
    2. 12.2 Layout Examples
    3. 12.3 Efficiency and Thermal Considerations
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントの更新通知を受け取る方法
    2. 13.2 コミュニティ・リソース
    3. 13.3 商標
    4. 13.4 静電気放電に関する注意事項
    5. 13.5 Glossary
  14. 14メカニカル、パッケージ、および注文情報

6 Pin Configuration and Functions

YZH Package
16-Pin DSBGA
Top View
RTJ Package
20-Pin WQFN
Top View

Pin Functions

PIN I/O DESCRIPTION
NAME DSBGA WQFN
AGND C3 18 I Analog ground
AVDD D2 9 I Analog supply (must be same voltage as PVDD)
G0 C2 15 I Gain select (LSB)
G1 B2 1 I Gain select (MSB)
INL– B1 19 I Left channel negative input
INL+ A1 20 I Left channel positive input
INR– C1 17 I Right channel negative input
INR+ D1 16 I Right channel positive input
NC — 6, 10 — No internal connection
OUTL– A4 5 O Left channel negative differential output
OUTL+ A3 2 O Left channel positive differential output
OUTR– D4 11 O Right channel negative differential output
OUTR+ D3 14 O Right channel positive differential output
PGND C4 4, 12 I Power ground
PVDD A2 3, 13 I Power supply (must be same voltage as AVDD)
SDL B4 7 I Left channel shutdown terminal (active low)
SDR B3 8 I Right channel shutdown terminal (active low)
Thermal Pad — — — Connect the thermal pad of WQFN package to PCB GND