JAJS401H november   2007  – april 2023 TPS74701

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Other Orderable Devices (non-M3 Suffix)
    6. 6.6  Electrical Characteristics: Orderable Device (M3 Suffix)
    7. 6.7  Typical Characteristics: VEN = VIN (All Other Orderable Devices, Non-M3 Suffix)
    8. 6.8  Typical Characteristics: VEN = VIN = 1.8 V, VOUT = 1.5 V (All Other Orderable Devices, Non-M3 Suffix)
    9. 6.9  Typical Characteristics: IOUT = 50 mA (M3 Suffix)
    10. 6.10 Typical Characteristics: VEN = VIN = 1.8 V, VOUT = 1.5 V (M3 Suffix)
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Programmable Soft-Start
      2. 7.3.2 Enable and Shutdown
      3. 7.3.3 Power Good
      4. 7.3.4 Internal Current Limit
      5. 7.3.5 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input, Output, and Bias Capacitor Requirements
      2. 8.1.2 Transient Response
      3. 8.1.3 Dropout Voltage
      4. 8.1.4 Sequencing Requirements
      5. 8.1.5 Output Noise
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Power Dissipation
        2. 8.4.1.2 Estimating Junction Temperature
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 Evaluation Module
        2. 9.1.1.2 Spice Models
      2. 9.1.2 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

GUID-756297F6-67D2-43A6-9850-FEBB3DD95933-low.gif Figure 5-1 DRC Package,10-Pin VSON(Top View)
Table 5-1 Pin Functions
PIN TYPE DESCRIPTION
NAME NO.
IN 1, 2 I Input to the device.
EN 5 I Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the regulator into shutdown mode. This pin must not be left unconnected.
SS 7 — Soft-start pin. A capacitor connected on this pin to ground sets the start-up time. If this pin is left unconnected, the regulator output soft-start ramp time is typically 200 μs.
BIAS 4 I Bias input voltage for error amplifier, reference, and internal control circuits.
PG 3 O Power-good pin. An open-drain, active-high output that indicates the status of VOUT. When VOUT exceeds the PG trip threshold, the PG pin goes into a high-impedance state. When VOUT is below this threshold the pin is driven to a low-impedance state. A pullup resistor from 10 kΩ to 1 MΩ must be connected from this pin to a supply of up to 5.5 V. The supply can be higher than the input voltage. Alternatively, the PG pin can be left unconnected if output monitoring is not necessary.
FB 8 I Feedback pin. The feedback connection to the center tap of an external resistor divider network that sets the output voltage. This pin must not be left floating.
OUT 9, 10 O Regulated output voltage. A small capacitor (total typical capacitance ≥ 2.2 μF, ceramic) is needed from this pin to ground to assure stability.
NC N/A I No connection. This pin can be left floating or connected to GND to allow better thermal contact to the top-side plane.
GND 6 I Ground
Thermal Pad — I Solder this pad to the ground plane for increased thermal performance.