JAJS498D August   2008  – August 2023 DAC5311 , DAC6311 , DAC7311

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements
    7. 7.7  Timing Diagrams
    8. 7.8  Typical Characteristics: AVDD = 5 V
    9. 7.9  Typical Characteristics: AVDD = 3.6 V
    10. 7.10 Typical Characteristics: AVDD = 2.7 V
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DAC Section
      2. 8.3.2 Resistor String
      3. 8.3.3 Output Amplifier
      4. 8.3.4 Power-On Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Modes
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1 Input Shift Register
        2. 8.5.1.2 SYNC Interrupt
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Microprocessor Interfacing
        1. 9.1.1.1 DACx311 to 8051 Interface
        2. 9.1.1.2 DACx311 to Microwire Interface
        3. 9.1.1.3 DACx311 to 68HC11 Interface
    2. 9.2 Typical Applications
      1. 9.2.1 Loop Powered Transmitter
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Using the REF5050 as a Power Supply for the DACx311
      3. 9.2.3 Bipolar Operation Using the DACx311
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 ドキュメントの更新通知を受け取る方法
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 用語集
  12. 11Mechanical, Packaging, and Orderable Information

7.5 Electrical Characteristics

at AVDD = 2.0 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, and TA = –40°C to +125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC PERFORMANCE(1)
DAC5311 Resolution 8 Bits
DAC6311 10 Bits
DAC7311 12 Bits
DAC5311 Relative accuracy Measured by the line passing through codes 3 and 252 ±0.01 ±0.25 LSB
DAC6311 Measured by the line passing through codes 12 and 1012 ±0.06 ±0.5 LSB
DAC7311 Measured by the line passing through codes 30 and 4050 ±0.3 ±1 LSB
DAC5311 Differential nonlinearity ±0.01 ±0.25 LSB
DAC6311 ±0.03 ±0.5 LSB
DAC7311 ±0.2 ±1 LSB
Offset error Measured by the line passing through two codes(2) ±0.05 ±4 mV
Offset error drift 3 μV/°C
Zero code error All zeros loaded to the DAC register 0.2 mV
Full-scale error All ones loaded to DAC register 0.04 0.2 % of FSR
Gain error 0.05 ±0.15 % of FSR
Gain temperature coefficient AVDD = 5 V ±0.5 ppm of FSR/°C
AVDD = 2.0 V ±1.5
OUTPUT CHARACTERISTICS
Output voltage range 0 AVDD V
Output voltage settling time(3) RL = 2 kΩ, CL = 200 pF, AVDD = 5 V,
1/4 scale to 3/4 scale		 6 10 μs

RL = 2 MΩ, CL = 470 pF 		12 μs
Slew rate 0.7 V/μs
Capacitive load stability RL = ∞ 470 pF
RL = 2 kΩ 1000 pF
Code change glitch impulse 1 LSB change around major carry 0.5 nV-s
Digital feedthrough 0.5 nV-s
Power-on glitch impulse RL = 2 kΩ, CL = 200 pF, AVDD = 5 V 17 mV
DC output impedance 0.5 Ω
Short circuit current AVDD = 5 V 50 mA
AVDD = 3 V 20 mA
Power-up time Coming out of power-down mode 50 μs
AC PERFORMANCE
SNR TA = 25°C, BW = 20 kHz, 12-bit level,
AVDD = 5 V, fOUT = 1 kHz, 1st 19 harmonics removed for SNR calculation		 81 dB
THD –65 dB
SFDR 65 dB
SINAD 65 dB
DAC output noise density(4) TA = 25°C, at zero-scale input,
fOUT = 1 kHz, AVDD = 5 V		 17 nV/√Hz
TA = 25°C, at mid-code input,
fOUT = 1 kHz, AVDD = 5 V		 110 nV/√Hz
DAC output noise(5) TA= +25°C, at mid-code input,
0.1 Hz to 10 Hz, AVDD = 5 V		 3 μVPP
LOGIC INPUTS(3)
Input current ±1 μA
VINL, Input low voltage AVDD = 2.7 V to 5.5 V 0.3 × AVDD V
AVDD = 2.0 V to 2.7 V 0.1 × AVDD V
VINH, Input high voltage AVDD = 2.7 V to 5.5 V 0.7 × AVDD V
AVDD = 2.0 V to 2.7 V 0.9 × AVDD V
Pin capacitance 1.5 3 pF
POWER REQUIREMENTS
AVDD 2.0 5.5 V
IDD Normal mode VINH = AVDD and VINL = GND, at midscale code(6) AVDD = 3.6 V to 5.5 V 110 180 μA
AVDD = 2.7 V to 3.6 V 95 150 μA
AVDD = 2.0 V to 2.7 V 80 140 μA
All power-down mode VINH = AVDD and VINL = GND, at midscale code(6) AVDD = 3.6 V to 5.5 V 0.5 3.5 μA
AVDD = 2.7 V to 3.6 V 0.4 3 μA
AVDD = 2.0 V to 2.7 V 0.1 2 μA
Power dissipation Normal mode VINH = AVDD and VINL = GND, at midscale code(6) AVDD = 3.6 V to 5.5 V 0.55 0.99 mW
AVDD = 2.7 V to 3.6 V 0.25 0.54 mW
AVDD = 2.0 V to 2.7 V 0.14 0.38 mW
All power-down mode VINH = AVDD and VINL = GND, at midscale code(6) AVDD = 3.6 V to 5.5 V 2.50 19.2 µW
AVDD = 2.7 V to 3.6 V 1.08 10.8 µW
AVDD = 2.0 V to 2.7 V 0.72 8.1 µW
(1) Linearity calculated using a reduced code range of 3 to 252 for 8-bit, 12 to 1012 for 10bit, and 30 to 4050 for 12-bit, output unloaded.
(2) Straight line passing through codes 3 and 252 for 8-bit, 12 and 1012 for 10-bit, and 30 and 4050 for 12-bit, output unloaded.
(3) Specified by design and characterization, not production tested.
(4) For more details, see Figure 7-23.
(5) For more details, see Figure 7-24.
(6) For more details, see Figure 7-16 and Figure 7-58.