JAJS498D August   2008  – August 2023 DAC5311 , DAC6311 , DAC7311

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements
    7. 7.7  Timing Diagrams
    8. 7.8  Typical Characteristics: AVDD = 5 V
    9. 7.9  Typical Characteristics: AVDD = 3.6 V
    10. 7.10 Typical Characteristics: AVDD = 2.7 V
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DAC Section
      2. 8.3.2 Resistor String
      3. 8.3.3 Output Amplifier
      4. 8.3.4 Power-On Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Modes
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1 Input Shift Register
        2. 8.5.1.2 SYNC Interrupt
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Microprocessor Interfacing
        1. 9.1.1.1 DACx311 to 8051 Interface
        2. 9.1.1.2 DACx311 to Microwire Interface
        3. 9.1.1.3 DACx311 to 68HC11 Interface
    2. 9.2 Typical Applications
      1. 9.2.1 Loop Powered Transmitter
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Using the REF5050 as a Power Supply for the DACx311
      3. 9.2.3 Bipolar Operation Using the DACx311
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 ドキュメントの更新通知を受け取る方法
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 用語集
  12. 11Mechanical, Packaging, and Orderable Information

8.5.1.2 SYNC Interrupt

In a normal write sequence, the SYNC line is kept low for at least 16 falling edges of SCLK and the DAC is updated on the 16th falling edge. However, bringing SYNC high before the 16th falling edge acts as an interrupt to the write sequence. The shift register is reset and the write sequence is seen as invalid. Neither an update of the DAC register contents nor a change in the operating mode occurs, as shown in Figure 8-4.

GUID-6DAACA12-D3F9-49F0-8E84-F7EC69EDF857-low.gif Figure 8-4 DACx311 SYNC Interrupt Facility