JAJS517E December   2009  – August 2016 ADS8331 , ADS8332

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Companion Products
  6. 6 Device Comparison
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics: VA = 2.7 V
    6. 8.6  Electrical Characteristics: VA = 5 V
    7. 8.7  Timing Requirements: VA = 2.7 V
    8. 8.8  Timing Characteristics: VA = 5 V
    9. 8.9  Typical Characteristics: DC Performance
    10. 8.10 Typical Characteristics: AC Performance
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Signal Conditioning
      2. 9.3.2 Analog Input
        1. 9.3.2.1 Driver Amplifier Choice
        2. 9.3.2.2 Bipolar to Unipolar Driver
    4. 9.4 Device Functional Modes
      1. 9.4.1 Reference
      2. 9.4.2 Converter Operation
        1. 9.4.2.1 Manual Channel Select Mode
        2. 9.4.2.2 Auto Channel Select Mode
        3. 9.4.2.3 Start of a Conversion
        4. 9.4.2.4 Status Output Pin (EOC/INT)
        5. 9.4.2.5 Power-Down Modes and Acquisition Time
    5. 9.5 Programming
      1. 9.5.1 Digital Interface
        1. 9.5.1.1 Internal Register
      2. 9.5.2 Writing to the Converter
        1. 9.5.2.1 Configuring the Converter and Default Mode
      3. 9.5.3 Reading the Configuration Register
      4. 9.5.4 Reading the Conversion Result
        1. 9.5.4.1 TAG Mode
        2. 9.5.4.2 Daisy-Chain Mode
      5. 9.5.5 Reset Function
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 ADC Reference Driver
        1. 10.1.1.1 Reference Driver Circuit for VREF = 4.096 V
        2. 10.1.1.2 Reference Driver Circuit for VREF=2.5 V, VA=2.7 V
      2. 10.1.2 ADC Input Driver
        1. 10.1.2.1 Input Amplifier Selection
        2. 10.1.2.2 ADC Input RC Filter
    2. 10.2 Typical Applications
      1. 10.2.1 DAQ Circuit for Low Noise and Distortion Performance for a 10-kHz Input Signal at 500 kSPS
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Ultra Low-Power DAQ Circuit for DC Input Signals at 10 kSPS per Channel
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
    2. 13.2 関連リンク
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

11 Power Supply Recommendations

During power on of the ADS833x, the digital interface supply voltage (VBD) should not exceed the analog supply voltage (VA). This condition is specified in the Power-Supply Requirements section of the Electrical Characteristics tables. If the analog and digital interface supplies for the converter are not generated by a single voltage source, TI recommends to power on the analog supply and wait for it to reach its final value before the digital interface supply is activated. Furthermore, the voltages applied to the analog input pins (INX, ADCIN) and digital input pins (RESET, FS/CS, SCLK, SDI, and CONVST) should not exceed the voltages on VA and VBD, respectively, during the power-on sequence. This requirement prevents these input pins from powering the ADS833x through the ESD protection diodes and circuitry, and causing an increase in current consumption, until both supplies are fully powered (see the Electrical Characteristics and Figure 34 for further details).

Communication with the ADS833x, such as initiating a conversion with CONVST or writing to the Configuration register, should not occur for a minimum of 2 μs after the analog and digital interface supplies have finished the power-on sequence and reached the respective final values in the system. This time is required for the internal POR to activate and place the digital core of the device into the default mode of operation. This minimum delay time must also be adhered to whenever a reset condition occurs (see the section for additional information).