JAJS517E December   2009  – August 2016 ADS8331 , ADS8332

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Companion Products
  6. 6 Device Comparison
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics: VA = 2.7 V
    6. 8.6  Electrical Characteristics: VA = 5 V
    7. 8.7  Timing Requirements: VA = 2.7 V
    8. 8.8  Timing Characteristics: VA = 5 V
    9. 8.9  Typical Characteristics: DC Performance
    10. 8.10 Typical Characteristics: AC Performance
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Signal Conditioning
      2. 9.3.2 Analog Input
        1. 9.3.2.1 Driver Amplifier Choice
        2. 9.3.2.2 Bipolar to Unipolar Driver
    4. 9.4 Device Functional Modes
      1. 9.4.1 Reference
      2. 9.4.2 Converter Operation
        1. 9.4.2.1 Manual Channel Select Mode
        2. 9.4.2.2 Auto Channel Select Mode
        3. 9.4.2.3 Start of a Conversion
        4. 9.4.2.4 Status Output Pin (EOC/INT)
        5. 9.4.2.5 Power-Down Modes and Acquisition Time
    5. 9.5 Programming
      1. 9.5.1 Digital Interface
        1. 9.5.1.1 Internal Register
      2. 9.5.2 Writing to the Converter
        1. 9.5.2.1 Configuring the Converter and Default Mode
      3. 9.5.3 Reading the Configuration Register
      4. 9.5.4 Reading the Conversion Result
        1. 9.5.4.1 TAG Mode
        2. 9.5.4.2 Daisy-Chain Mode
      5. 9.5.5 Reset Function
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 ADC Reference Driver
        1. 10.1.1.1 Reference Driver Circuit for VREF = 4.096 V
        2. 10.1.1.2 Reference Driver Circuit for VREF=2.5 V, VA=2.7 V
      2. 10.1.2 ADC Input Driver
        1. 10.1.2.1 Input Amplifier Selection
        2. 10.1.2.2 ADC Input RC Filter
    2. 10.2 Typical Applications
      1. 10.2.1 DAQ Circuit for Low Noise and Distortion Performance for a 10-kHz Input Signal at 500 kSPS
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Ultra Low-Power DAQ Circuit for DC Input Signals at 10 kSPS per Channel
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
    2. 13.2 関連リンク
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

7 Pin Configuration and Functions

PW Package
24-Pin TSSOP
Top View
ADS8331 ADS8332 po_pw_bas363.gif
RGE Package
24-Pin VQFN With Exposed Thermal Pad
Top View
ADS8331 ADS8332 po_rge_bas363.gif
1. NC = No internal connection (ADS8331 only).
2. Connect thermal pad to analog ground.
3. NC = No internal connection (ADS8331 only).

Pin Functions: ADS8331

PIN I/O DESCRIPTION
NAME TSSOP VQFN
ADCIN 21 18 I ADC input
AGND 20 17 — Analog ground
DGND 14 11 — Digital interface ground
COM 23 20 I Common ADC input (usually connected to AGND)
CONVST 15 12 I Conversion start. Freezes sample and hold, starts conversion.
EOC/INT/CDI 9 6 O/O/I Status output. If programmed as end-of-conversion (EOC), this pin is low (default) when a conversion is in progress. If programmed as an interrupt (INT), this pin is low (default) after the end of conversion and returns high after FS/CS goes low. The polarity of EOC or INT is programmable.
This pin can also be used as a chain data input (CDI) when operated in daisy-chain mode.
FS/CS 11 8 I Frame sync signal for DSP (such as TMS320™ DSP) or chip select input for SPI.
IN[0:3] 1-3, 24 21-24 I Mux inputs
NC 4-7 1-4 — No connection
MUXOUT 22 19 O Mux output
REF+ 18 15 I External reference input
REF– 19 16 — External reference ground (connect to AGND through an individual via on the printed-circuit-board)
RESET 8 5 I External reset (active low)
SCLK 10 7 I SPI clock for serial interface
SDI 12 9 I SPI serial data in
SDO 13 10 O SPI serial data out
VA 17 14 — Analog supply, 2.7 V to 5.5 V
VBD 16 13 — Digital interface supply

Pin Functions: ADS8332

PIN I/O DESCRIPTION
NAME TSSOP VQFN
ADCIN 21 18 I ADC input
AGND 20 17 — Analog ground
DGND 14 11 — Digital interface ground
COM 23 20 I Common ADC input (usually connected to AGND)
CONVST 15 12 I Conversion start. Freezes sample and hold, starts conversion.
EOC/INT/CDI 9 6 O/O/I Status output. If programmed as end-of-conversion (EOC), this pin is low (default) when a conversion is in progress. If programmed as an interrupt (INT), this pin is low (default) after the end of conversion and returns high after FS/CS goes low. The polarity of EOC or INT is programmable.
This pin can also be used as a chain data input (CDI) when operated in daisy-chain mode.
FS/CS 11 8 I Frame sync signal for DSP (such as TMS320™ DSP) or chip select input for SPI.
IN[0:7] 1-7, 24 1-4, 21-24 I Mux inputs
MUXOUT 22 19 O Mux output
REF+ 18 15 I External reference input
REF– 19 16 — External reference ground (connect to AGND through an individual via on the printed-circuit-board)
RESET 8 5 I External reset (active low)
SCLK 10 7 I SPI clock for serial interface
SDI 12 9 I SPI serial data in
SDO 13 10 O SPI serial data out
VA 17 14 — Analog supply, 2.7 V to 5.5 V
VBD 16 13 — Digital interface supply