JAJS529A December   2010  – October 2016 TPS53310

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Soft Start
      2. 7.3.2 Power Good
      3. 7.3.3 Undervoltage Lockout (UVLO) Function
      4. 7.3.4 Overcurrent Protection
      5. 7.3.5 Overvoltage Protection
      6. 7.3.6 Undervoltage Protection
      7. 7.3.7 Overtemperature Protection
      8. 7.3.8 Output Discharge
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation Mode
      2. 7.4.2 Eco-mode™ Light-Load Operation
      3. 7.4.3 Forced Continuous Conduction Mode (FCCM)
    5. 7.5 Programming
      1. 7.5.1 Master/Slave Operation and Synchronization
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Determine the Value of R1 and R2
        2. 8.2.2.2 Choose the Inductor
        3. 8.2.2.3 Choose the Output Capacitor(s)
        4. 8.2.2.4 Choose the Input Capacitor
        5. 8.2.2.5 Compensation Design
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

5 Pin Configuration and Functions

RGT Package
16-Pin VQFN
Top View

Pin Functions

PIN TYPE(1) DESCRIPTION
NO. NAME
1 EN I Enable. Internally pulled up to VDD with a 1.35-MΩ resistor.
2 SYNC B Synchronization signal for input interleaving. Master SYNC pin sends out 180° out-of-phase signal to slave SYNC. SYNC frequency must be within ±20% of slave nominal frequency.
3 PGD O Power good output flag; Open drain output. Pull up to an external rail through a resistor.
4 VBST P Supply input for high-side MOSFET (bootstrap terminal); Connect capacitor from this pin to SW terminal.
5 SW B Output inductor connection to integrated power devices
6 SW B Output inductor connection to integrated power devices
7 SW B Output inductor connection to integrated power devices
8 PS I Mode configuration pin (with 10 µA current):
Connecting to ground: Forced CCM slave
Pulled high or floating (internal pulled high): Forced CCM master
Connect with 24.3 kΩ to GND: DE slave
Connect with 57.6 kΩ to GND: HEF mode
Connect with 105 kΩ to GND: reserved mode
Connect with 174 kΩ to GND: DE master
9 COMP O Error amplifier compensation terminal; Type III compensation method is recommended for stability.
10 FB I Voltage feedback (also used for OVP, UVP and PGD determination)
11 AGND G Device analog ground terminal
12 VDD P Input bias supply for analog functions
13 VIN P Gate driver supply and power conversion voltage
14 VIN P Gate driver supply and power conversion voltage
15 PGND P Power ground terminal
16 PGND P Power ground terminal
(1) B = Bidirectional, G = Ground, I = Input, O = Output, P = Supply