JAJS533E
November 2010 – August 2023
ISO35T
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Power Ratings
6.6
Insulation Specifications
6.7
Safety-Related Certifications
6.8
Safety Limiting Values
6.9
Electrical Characteristics: Driver
6.10
Electrical Characteristics: Receiver
6.11
Supply Current
6.12
Transformer Driver Characteristics
6.13
Switching Characteristics: Driver
6.14
Switching Characteristics: Receiver
6.15
Insulation Characteristics Curves
6.16
Typical Characteristics
7
Parameter Measurement Information
26
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Device Functional Modes
8.3.1
Device I/O Schematics
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Transient Voltages
9.2.3
Application Curve
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Documentation Support
12.1.1
Related Documentation
12.2
Community Resources
12.3
Trademarks
12.4
静電気放電に関する注意事項
12.5
用語集
13
Mechanical, Packaging, and Orderable Information
Figure 7-1
Driver V
OD
Test and Current Definitions
Figure 7-2
Driver V
OD
With Common-Mode Loading Test Circuit
Figure 7-3
Test Circuit and Waveform Definitions For The Driver Common-Mode Output Voltage
Figure 7-4
Driver Short-Circuit Test Circuit and Waveforms (Short Circuit applied at Time t=0
Figure 7-5
Driver Switching Test Circuit and Voltage Waveforms
Figure 7-6
Driver High-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
Figure 7-7
Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveform
Figure 7-8
Receiver Voltage and Current Definitions
Figure 7-9
Receiver Switching Test Circuit and Waveforms
Figure 7-10
Receiver Enable Test Circuit and Waveforms, Data Output High
Figure 7-11
Receiver Enable Test Circuit and Waveforms, Data Output Low
Figure 7-12
Transient Over-Voltage Test Circuit
Figure 7-13
Common-Mode Transient Immunity Test Circuit
Figure 7-14
Transition Times and Break-Before-Make Time Delay for D1, D2 Outputs