BQ24650 デバイスは高集積のスイッチ・モード・バッテリ充電コントローラです。入力電圧レギュレーションにより、入力電圧が設定値を下回った場合、充電電流を減らします。入力が太陽光パネルで駆動されている場合には、入力レギュレーション・ループによって、太陽光パネルが最大の出力電力を供給できるよう充電電流を減らします。
BQ24650 は固定周波数同期整流 PWM コントローラに加え、高精度の電流および電圧レギュレーション、充電プリコンディショニング、充電終了、充電ステータス監視機能を備えています。
型番 | パッケージ | 本体サイズ(公称) |
---|---|---|
BQ24650 | VQFN (16) | 3.50mm×3.50mm |
Changes from A Revision (April 2016) to B Revision
Changes from * Revision (July 2010) to A Revision
BQ24650 は、プリコンディショニング、定電流、定電圧の 3 つのフェーズでバッテリを充電します。電流が高速充電レートの 1/10 に達すると、充電は終了します。プリチャージ・タイマは 30 分に固定されています。BQ24650 は、バッテリ電圧が内部スレッショルドを下回ると充電サイクルを自動的に再開し、入力電圧がバッテリ電圧を下回ると低静止電流スリープ・モードに移行します。
BQ24650 は、帰還基準電圧 VFB を 2.1V に設定した状態で 2.1V~26V のバッテリをサポートしています。充電電流は、適切な検出抵抗を選択することでプログラムされます。BQ24650 は 16 ピン、3.5mm × 3.5mm2 の薄型 QFN パッケージで供給されます。
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | VCC | P | IC power positive supply. Place a 1-μF ceramic capacitor from VCC to GND and place it as close as possible to IC. Place a 10-Ω resistor from input side to VCC pin to filter the noise. |
2 | MPPSET | I | Input voltage set point. Use a voltage divider from input source to GND to set voltage on MPPSET to 1.2 V. To disable charge, pull MPPSET below 75 mV. |
3 | STAT1 | O | Open-drain charge status output to indicate various charger operation. Connect to the cathode of LED with 10 kΩ to the pullup rail. LOW or LED light up indicates charge in progress. Otherwise stays HI or LED stays off. When any fault condition occurs, both STAT1 and STAT2 are HI, or both LEDs are off. |
4 | TS | I | Temperature qualification voltage input. Connect to a negative temperature coefficient thermistor. Program the hot and cold temperature window with a resistor divider from VREF to TS to GND. A 103AT-2 thermister is recommended. |
5 | STAT2 | O | Open-drain charge status output to indicate various charger operation. Connect to the cathode of LED with 10 kΩ to the pullup rail. LOW or LED light up indicates charge is complete. Otherwise, stays HI or LED stays off. When any fault condition occurs, both STAT1 and STAT2 are HI, or both LEDs are off. |
6 | VREF | P | 3.3-V reference voltage output. Place a 1-μF ceramic capacitor from VREF to GND pin close to the IC. This voltage could be used for programming voltage on TS and the pullup rail of STAT1 and STAT2. |
7 | TERM_EN | I | Charge termination enable. Pull TERM_EN to GND to disable charge termination. Pull TERM_EN to VREF to allow charge termination. TERM_EN must be terminated and cannot be left floating. |
8 | VFB | I | Charge voltage analog feedback adjustment. Connect the output of a resistor divider powered from the battery terminals to this node to adjust the output battery voltage regulation. |
9 | SRN | I | Charge current sense resistor, negative input. A 0.1-μF ceramic capacitor is placed from SRN to SRP to provide differential-mode filtering. An optional 0.1-μF ceramic capacitor is placed from SRN to GND for common-mode filtering. |
10 | SRP | P/I | Charge current sense resistor, positive input. A 0.1-μF ceramic capacitor is placed from SRN to SRP to provide differential-mode filtering. A 0.1-μF ceramic capacitor is placed from SRP to GND for common-mode filtering. |
11 | GND | P | Power ground. Ground connection for high-current power converter node. On PCB layout, connect directly to source of low-side power MOSFET, to ground connection of input and output capacitors of the charger. Only connect to GND through the thermal pad underneath the IC. |
12 | REGN | P | PWM low-side driver positive 6-V supply output. Connect a 1-μF ceramic capacitor from REGN to GND, close to the IC. Use to drive low-side driver and high-side driver bootstrap Schottky diode from REGN to BTST. |
13 | LODRV | O | PWM low-side driver output. Connect to the gate of the low-side N-channel power MOSFET with a short trace. |
14 | PH | P | Switching node, charge current output inductor connection. Connect the 0.1-μF bootstrap capacitor from PH to BTST. |
15 | HIDRV | O | PWM high-side driver output. Connect to the gate of the high-side N-channel power MOSFET with a short trace. |
16 | BTST | P | PWM high-side driver positive supply. Connect the 0.1-µF bootstrap capacitor from PH to BTST. |
— | Thermal Pad | — | Exposed pad beneath the IC. The thermal pad must always be soldered to the board and have the vias on the thermal pad plane star-connecting to GND and ground plane for high-current power converter. It also serves as a thermal pad to dissipate heat. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Voltage (with respect to GND) | VCC, STAT1, STAT2, SRP, SRN | –0.3 | 33 | V |
PH | –2 | 36 | ||
VFB | –0.3 | 16 | ||
REGN, LODRV, TS, MPPSET, TERM_EN | –0.3 | 7 | ||
BTST, HIDRV with respect to GND | –0.3 | 39 | ||
VREF | –0.3 | 3.6 | ||
Maximum difference voltage | SRP–SRN | –0.5 | 0.5 | V |
Junction temperature, TJ | –40 | 155 | °C | |
Storage temperature, Tstg | –55 | 155 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Voltage range (with respect to GND) | VCC, STAT1, STAT2, SRP, SRN | –0.3 | 28 | V |
PH | –2 | 30 | ||
VFB | –0.3 | 14 | ||
REGN, LODRV, TS, MPPSET, TERM_EN | –0.3 | 6.5 | ||
BTST, HIDRV with respect to GND | –0.3 | 34 | ||
VREF | 3.3 | |||
Maximum difference voltage | SRP–SRN | –0.2 | 0.2 | V |
Junction temperature, TJ | –40 | 125 | °C |
THERMAL METRIC(1) | BQ24650 | UNIT | |
---|---|---|---|
RVA (VQFN) | |||
16 PINS | |||
RθJA | Junction-to-ambient thermal resistance(2) | 43.8 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 81 | °C/W |
RθJB | Junction-to-board thermal resistance | 16 | °C/W |
ψJT | Junction-to-top characterization parameter(3) | 0.6 | °C/W |
ψJB | Junction-to-board characterization parameter(4) | 15.77 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 4 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
OPERATING CONDITIONS | ||||||
VVCC_OP | VCC input voltage operating range | 5 | 28 | V | ||
QUIESCENT CURRENTS | ||||||
IBAT | Total battery discharge current (sum of currents into VCC, BTST, PH, SRP, SRN, VFB), VFB ≤ 2.1V | VCC < VBAT, VCC > VUVLO (SLEEP) | 15 | µA | ||
Battery discharge current (sum of currents into BTST, PH, SRP, SRN, VFB), VFB ≤ 2.1V | VCC > VBAT, VCC > VUVLO, CE = LOW | 5 | µA | |||
VCC > VBAT, VCC > VVCCLOWV,
CE = HIGH, Charge done |
5 | µA | ||||
IAC | Adapter supply current (sum of current into VCC pin) | VCC > VBAT, VCC > VUVLO, CE = LOW | 0.7 | 1 | mA | |
VCC > VBAT, VCC > VVCCLOWV,
CE = HIGH, charge done |
2 | 3 | mA | |||
VCC > VBAT, VCC > VVCCLOWV,
CE = HIGH, Charging, Qg_total = 10 nC [1] |
25 | mA | ||||
CHARGE VOLTAGE REGULATION | ||||||
VREG | Feedback regulation voltage | 2.1 | V | |||
Charge voltage regulation accuracy | TJ = 0°C to 85°C | –0.5% | 0.5% | |||
TJ = –40°C to 125°C | –0.7% | 0.7% | ||||
IVFB | Leakage current into VFB pin | VFB = 2.1 V | 100 | nA | ||
CURRENT REGULATION – FAST CHARGE | ||||||
VIREG_CHG | SRP-SRN current sense voltage range | VIREG_CHG = VSRP – VSRN | 40 | mV | ||
Charge current regulation accuracy | VIREG_CHG = 40 mV | –3% | 3% | |||
CURRENT REGULATION – PRE-CHARGE | ||||||
VPRECHG | Precharge current sense voltage range | VIREG_PRCHG = VSRP – VSRN | 4 | mV | ||
Precharge current regulation accuracy | VIREG_PRECH = 4 mV | –25% | 25% | |||
CHARGE TERMINATION | ||||||
VTERMCHG | Termination current sense voltage range | VITERM = VSRP – VSRN | 4 | mV | ||
Termination current accuracy | VITERM = 4 mV | –25% | 25% | |||
Deglitch time for termination (both edges) | 100 | ms | ||||
tQUAL | Termination qualification time | VBAT > VRECH and ICHG < ITERM | 250 | ms | ||
IQUAL | Termination qualification current | Discharge current once termination is detected | 2 | mA | ||
INPUT VOLTAGE REGULATION | ||||||
VMPPSET | MPPSET regulation voltage | 1.2 | V | |||
Input voltage regulation accuracy | –0.6% | 0.6% | ||||
IMPPSET | Leakage current into MPPSET pin | VMPPSET = 7 V, TA = 0 – 85°C | 1 | µA | ||
VMPPSET_CD | MPPSET shorted to disable charge | 75 | mV | |||
VMPPSET_CE | MPPSET released to enable charge | 175 | mV | |||
INPUT UNDERVOLTAGE LOCKOUT COMPARATOR (UVLO) | ||||||
VUVLO | AC undervoltage rising threshold | Measure on VCC | 3.65 | 3.85 | 4 | V |
VUVLO_HYS | AC undervoltage hysteresis, falling | 350 | mV | |||
VCC LOWV COMPARATOR | ||||||
VVCC LOWV_fall | Falling threshold, disable charge | Measure on VCC | 4.1 | V | ||
VVCC LOWV_rise | Rising threshold, resume charge | 4.35 | V | |||
SLEEP COMPARATOR (REVERSE DISCHARGING PROTECTION) | ||||||
VSLEEP _FALL | SLEEP falling threshold | VVCC – VSRN to enter SLEEP | 40 | 100 | 150 | mV |
VSLEEP_HYS | SLEEP hysteresis | 500 | mV | |||
SLEEP rising shutdown deglitch | VCC falling below SRN | 100 | ms | |||
SLEEP falling powerup deglitch | VCC rising above SRN, Delay to exit SLEEP mode | 30 | ms | |||
BAT LOWV COMPARATOR | ||||||
VLOWV | Precharge to fast charge transition (LOWV threshold) | Measure on VFB pin | 1.54 | 1.55 | 1.56 | V |
VLOWV_HYS | LOWV hysteresis | 100 | mV | |||
LOWV rising deglitch | VFB falling below VLOWV | 25 | ms | |||
LOWV falling deglitch | VFB rising above VLOWV + VLOWV_HYS | 25 | ms | |||
RECHARGE COMPARATOR | ||||||
VRECHG | Recharge threshold (with respect to VREG) | Measure on VFB pin | 35 | 50 | 65 | mV |
Recharge rising deglitch | VFB decreasing below VRECHG | 10 | ms | |||
Recharge falling deglitch | VFB increasing above VRECHG | 10 | ms | |||
BAT OVERVOLTAGE COMPARATOR | ||||||
VOV_RISE | Overvoltage rising threshold | As percentage of VFB | 104% | |||
VOV_FALL | Overvoltage falling threshold | As percentage of VFB | 102% | |||
INPUT OVERVOLTAGE COMPARATOR (ACOV) | ||||||
VACOV | AC overvoltage rising threshold on VCC | 31 | 32 | 33 | V | |
VACOV_HYS | AC overvoltage falling hysteresis | 1 | V | |||
AC overvoltage deglitch (both edges) | Delay to changing the STAT pins | 1 | ms | |||
AC overvoltage rising deglitch | Delay to disable charge | 1 | ms | |||
AC overvoltage falling deglitch | Delay to resume charge | 20 | ms | |||
THERMAL SHUTDOWN COMPARATOR | ||||||
TSHUT | Thermal shutdown rising temperature | Temperature increasing | 145 | °C | ||
TSHUT_HYS | Thermal shutdown hysteresis | 15 | °C | |||
Thermal shutdown rising deglitch | Temperature increasing | 100 | µs | |||
Thermal shutdown falling deglitch | Temperature decreasing | 10 | ms | |||
THERMISTOR COMPARATOR | ||||||
VLTF | Cold temperature rising threshold | As percentage to VVREF | 72.5% | 73.5% | 74.5% | |
VLTF_HYS | Rising hysteresis | 0.2% | 0.4% | 0.6% | ||
VHTF | Hot temperature rising threshold | 46.7% | 47.5% | 48.3% | ||
VTCO | Cut-off temperature rising threshold | 44.3% | 45% | 45.7% | ||
Deglitch time for temperature out of range detection | VTS < VLTF, or VTS < VTCO, or
VTS < VHTF |
400 | ms | |||
Deglitch time for temperature in valid range detection | VTS > VLTF – VLTF_HYS or VTS >VTCO, or VTS > VHTF | 20 | ms | |||
CHARGE OVERCURRENT COMPARATOR (CYCLE-BY-CYCLE) | ||||||
VOC | Charge overcurrent rising threshold | Current rising, in synchronous mode measure (VSRP – VSRN) | 80 | mV | ||
CHARGE UNDERCURRENT COMPARATOR (CYCLE-BY-CYCLE) | ||||||
VISYNSET | Charge undercurrent falling threshold | Switch from CCM to DCM, VSRP > 2.2V | 1 | 5 | 9 | mV |
BATTERY-SHORTED COMPARATOR (BATSHORT) | ||||||
VBATSHT | BAT short falling threshold, forced non-synchronous mode | VSRP falling | 2 | V | ||
VBATSHT_HYS | BAT short rising hysteresis | 200 | mV | |||
tBATSHT_DEG | Deglitch on both edges | 1 | µs | |||
LOW CHARGE CURRENT COMPARATOR | ||||||
VLC | Low charge current falling threshold | Measure V(SRP-SRN) | 1.25 | mV | ||
VLC_HYS | Low charge current rising hysteresis | 1.25 | mV | |||
tLC_DEG | Deglitch on both edges | 1 | µs | |||
VREF REGULATOR | ||||||
VVREF_REG | VREF regulator voltage | VVCC > VUVLO, 0 – 35 mA load | 3.267 | 3.3 | 3.333 | V |
IVREF_LIM | VREF current limit | VVREF = 0 V, VVCC > VUVLO | 35 | mA | ||
REGN REGULATOR | ||||||
VREGN_REG | REGN regulator voltage | VVCC > 10 V, MPPSET > 175 mV | 5.7 | 6.0 | 6.3 | V |
IREGN_LIM | REGN current limit | VREGN = 0 V, VVCC > VUVLO, MPPSET < 75 mV | 40 | mA | ||
BATTERY DETECTION | ||||||
tWAKE | Wake timer | Max time charge is enabled | 500 | ms | ||
IWAKE | Wake current | RSENSE = 10 mΩ | 50 | 125 | 200 | mA |
tDISCHARGE | Discharge timer | Max time discharge current is applied | 1 | sec | ||
IDISCHARGE | Discharge current | 6 | mA | |||
IFAULT | Fault current after a timeout fault | 2 | mA | |||
IQUAL | Termination qualification current | 2 | mA | |||
tQUAL | Termination qualification time | 250 | ms | |||
VWAKE | Wake threshold (with respect to VREG) | Voltage on VFB to detect battery absent during wake | 50 | mV | ||
VDISCH | Discharge threshold | Voltage on VFB to detect battery absent during discharge | 1.55 | V | ||
PWM HIGH-SIDE DRIVER (HIDRV) | ||||||
RDS_HI_ON | High-side driver (HSD) turnon resistance | VBTST – VPH = 5.5 V | 3.3 | 6 | Ω | |
RDS_HI_OFF | High-side driver turnoff resistance | 1 | 1.4 | Ω | ||
VBTST_REFRESH | Bootstrap refresh comparator threshold Voltage | VBTST – VPH when low side refresh pulse is requested | 4.0 | 4.2 | V | |
PWM LOW-SIDE DRIVER (LODRV) | ||||||
RDS_LO_ON | Low-side driver (LSD) turn-on resistance | 4.1 | 7 | Ω | ||
RDS_LO_OFF | Low-side driver turn-off resistance | 1 | 1.4 | Ω | ||
PWM DRIVERS TIMING | ||||||
Driver dead-time | Dead time when switching between LSD and HSD, No load at LSD and HSD | 30 | ns | |||
PWM OSCILLATOR | ||||||
VRAMP_HEIGHT | PWM ramp height | As percentage of VCC | 7% | |||
PWM switching frequency | 510 | 600 | 690 | kHz | ||
INTERNAL SOFT START (8 STEPS TO REGULATION CURRENT ICHG) | ||||||
Soft-start steps | 8 | step | ||||
Soft-start step time | 1.6 | ms | ||||
CHARGER SECTION POWER-UP SEQUENCING | ||||||
Charge-enable delay after power-up | Delay from MPPSET > 175 mV to charger is allowed to turn on | 1.5 | s | |||
LOGIC IO PIN CHARACTERISTICS (STAT1, STAT2, TERM_EN) | ||||||
VOUT_LOW | STAT1, STAT2 output low saturation voltage | Sink current = 5 mA | 0.5 | V | ||
IOUT_HI | Leakage current | V = 32 V | 1.2 | µA | ||
VIN_LOW | TERM_EN input low threshold voltage | 0.4 | V | |||
VIN_HI | TERM_EN input high threshold voltage | 1.6 | V | |||
IIN_BIAS | TERM_EN bias current | VTERM_EN = 0.5 V | 60 | µA |
The BQ24650 is a highly integrated solar input Li-ion or Li-polymer battery charge controller.
The BQ24650 uses a high accuracy voltage regulator for the charging voltage. The charge voltage is programmed through a resistor divider from the battery to ground, with the midpoint tied to the VFB pin. The voltage at the VFB pin is regulated to 2.1 V, giving Equation 1 for the regulation voltage:
where
Li-Ion, LiFePO4, and sealed lead acid are widely used battery chemistries. Most commercial Li-ion cells can now be charged to 4.2 V/cell. A LiFePO4 battery allows a much higher charge and discharge rate, but the energy density is lower. The typical cell voltage is 3.6 V. The charge profile of both Li-Ion and LiFePO4 is preconditioning, constant current, and constant voltage. For maximum cycle life, the end-of-charge voltage threshold could be lowered to 4.1 V/cell.
Although the energy density is much lower than Li-based chemistry, lead acid is still popular due to its low manufacturing cost and high discharge rates. The typical voltage limit is from 2.3 V to 2.45 V. After the battery has been fully charged, a float charge is required to compensate for the self-discharge. The float charge limit is 100 mV to 200 mV below the constant voltage limit.
A solar panel has a unique point on the V-I or V-P curve, called the Maximum Power Point (MPP), at which the entire photovoltaic (PV) system operates with maximum efficiency and produces its maximum output power. The constant voltage algorithm is the simplest Maximum Power Point Tracking (MPPT) method. The BQ24650 automatically reduces charge current so the maximum power point is maintained for maximum efficiency.
If the solar panel or other input source cannot provide the total power of the system and BQ24650 charger, the input voltage drops. When the voltage sensed on the MPPSET pin drops below 1.2 V, the charger maintains the input voltage by reducing the charge current. If the MPPSET pin voltage is forced below 1.2 V, the BQ24650 stays in the input voltage regulation loop while the output current is zero. The STAT1 pin is LOW and STAT2 pin is HIGH.
The voltage at the MPPSET pin is regulated to 1.2 V, giving Equation 2 for the regulation voltage:
The MPPSET pin is also used as charge enable control. If the voltage on MPPSET is pulled down below 75 mV, charge is disabled. Charge resumes if the voltage on MPPSET goes back above 175 mV.
Battery current is sensed by resistor RSR connected between SRP and SRN. The full-scale differential voltage between SRP and SRN is fixed at 40 mV. Thus, for a 20-mΩ sense resistor, the charging current is 2 A. For charging current, refer to Equation 3:
On power-up, if the battery voltage is below the VLOWV threshold, the BQ24650 applies the precharge current to the battery. This feature is intended to revive deeply discharged cells. If the VLOWV threshold is not reached within 30 minutes of initiating precharge, the charger turns off and a FAULT is indicated on the status pins.
The precharge current is determined as 1/10 of the fast charge current according to Equation 4:
The BQ24650 monitors the charging current during the voltage regulation phase. Termination is detected while the voltage on the VFB pin is higher than the VRECH threshold and the charge current is less than the ITERM threshold (1/10 of fast charge current), as calculated in Equation 5:
A new charge cycle is initiated when one of the following conditions occurs:
The TERM_EN pin may be taken LOW to disable termination. If TERM_EN is pulled above 1.6 V, the BQ24650 allows termination.
The BQ24650 uses a SLEEP comparator to determine the source of power on the VCC pin, because VCC can be supplied either from a battery or an adapter. If the VCC voltage is greater than the SRN voltage, and all other conditions are met for charging, the BQ24650 then attempts to charge a battery (see Enable and Disable Charging). If SRN voltage is greater than VCC, indicating that a battery is the power source, the BQ24650 enters low quiescent current (< 15 µA) SLEEP mode to minimize current drain from the battery.
If VCC is below the UVLO threshold, the device is disabled, and VREF LDO turns off.
The following conditions have to be valid before charging is enabled:
One of the following conditions stops on-going charging:
The charger automatically soft-starts the charger regulation current every time the charger goes into fast-charge to ensure there is no overshoot or stress on the output capacitors or the power converter. The soft-start consists of stepping-up the charge regulation current into 8 evenly divided steps up to the programmed charge current. Each step lasts approximately 1.6 ms, for a typical rise time of 13 ms. No external components are needed for this function.
The synchronous buck PWM converter uses a fixed frequency voltage mode with feed-forward control scheme. A type III compensation network allows using ceramic capacitors at the output of the converter. The compensation input stage is connected internally between the feedback output (FBO) and the error amplifier input (EAI). The feedback compensation stage is connected between the error amplifier input (EAI) and error amplifier output (EAO). The LC output filter must be selected to give a resonant frequency of 12 kHz – 17 kHz for the BQ24650, where resonant frequency, fo, is given by:
An internal saw-tooth ramp is compared to the internal EAO error control signal to vary the duty-cycle of the converter. The ramp height is 7% of the input adapter voltage making it always directly proportional to the input adapter voltage. This cancels out any loop gain variation due to a change in input voltage and simplifies the loop compensation. The ramp is offset by 300 mV to allow zero percent duty-cycle when the EAO signal is below the ramp. The EAO signal is also allowed to exceed the saw-tooth ramp signal in order to get a 100% duty-cycle PWM request. Internal gate drive logic allows achieving 99.98% duty-cycle while ensuring the N-channel upper device always has enough voltage to stay fully on. If the BTST pin to PH pin voltage falls below 4.2 V for more than 3 cycles, then the high-side N-channel power MOSFET is turned off and the low-side N-channel power MOSFET is turned on to pull the PH node down and recharge the BTST capacitor. Then the high-side driver returns to 100% duty-cycle operation until the (BTST-PH) voltage is detected to fall low again due to leakage current discharging the BTST capacitor below 4.2 V, and the reset pulse is reissued.
The fixed-frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage, battery voltage, charge current, and temperature, simplifying output filter design and keeping it out of the audible noise region.
The charger operates in synchronous mode when the SRP-SRN voltage is above 5 mV (0.5-A inductor current for a 10-mΩ sense resistor). During synchronous mode, the internal gate drive logic ensures there is break-before-make complimentary switching to prevent shoot-through currents. During the 30-ns dead time where both FETs are off, the body-diode of the low-side power MOSFET conducts the inductor current. Having the low-side FET turn on keeps power dissipation low, and allows safe charging at high currents. During synchronous mode the inductor current is always flowing and the converter operates in continuous conduction mode (CCM), creating a fixed two-pole system.
The charger operates in non-synchronous mode when the SRP-SRN voltage is below 5 mV (0.5-A inductor current for a 10-mΩ sense resistor). In addition, the charger is forced into non-synchronous mode when battery voltage is lower than 2 V or when the average SRP-SRN voltage is lower than 1.25 mV.
During non-synchronous operation, the body-diode of the low-side MOSFET can conduct the positive inductor current after the low-side N-channel power MOSFET turns off. When the load current decreases and the inductor current drops to zero, the body diode is naturally turned off and the inductor current becomes discontinuous. This mode is called Discontinuous Conduction Mode (DCM). During DCM, the low-side N-channel power MOSFET turns on when the bootstrap capacitor voltage drops below 4.2 V, then the low-side power MOSFET turns off and stays off until the beginning of the next cycle, where the high-side power MOSFET is turned on again. The low-side MOSFET on time is required to ensure the bootstrap capacitor is always recharged and able to keep the high-side power MOSFET on during the next cycle. This is important for battery chargers, where unlike regular DC-DC converters, there is a battery load that maintains a voltage and can both source and sink current. The low-side pulse pulls the PH node (connection between high and low-side MOSFETs) down, allowing the bootstrap capacitor to recharge up to the REGN LDO value. After the refresh pulse, the low-side MOSFET is kept off to prevent negative inductor current from occurring.
At very low currents during non-synchronous operation, there may be a small amount of negative inductor current during the recharge pulse. The charge must be low enough to be absorbed by the input capacitance. Whenever the converter goes into zero percent duty-cycle, the high-side MOSFET does not turn on, and the low-side MOSFET does not turn on (except for recharge pulse) either, and there is almost no discharge from the battery.
During DCM mode the loop response automatically changes and has a single pole system at which the pole is proportional to the load current, because the converter does not sink current, and only the load provides a current sink. This means at very low currents the loop response is slower, as there is less sinking current available to discharge the output voltage.
In the BQ24650, if the SRP-SRN voltage decreases below 5 mV, the low-side FET is turned off for the remainder of the switching cycle to prevent negative inductor current. During DCM, the low-side FET only turns on when the bootstrap capacitor voltage drops below 4.2 V to provide refresh charge for the bootstrap capacitor. This is important to prevent negative inductor current from causing a boost effect in which the input voltage increases as power is transferred from the battery to the input capacitors and lead to an overvoltage stress on the VCC node and potentially cause damage to the system.